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ST touts F-2 with 'ART Accelerator', Cortex-M4, -M0 plans

Posted: 06 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:ARM Cortex M4? M0? 32-bit? MCU?

STMicroelectronics combined the launch of its new STM32 F-2 series, which hits 150DMIPS when executing code from Flash at 120Mhz, with the announcement of its roadmap for MCUs based on ARM Cortex-M4 and CM0 cores, due for release in 2011.

There are 30 new devices in the STM32 F-2 series, which targets high-performance, power sensitive applications particularly in consumer and mobile, due to its performance, 1.65V support, audio-class architecture, and small WLCSP64 package. It is also intended for industrial and medical apps, as the series touts rich connectivity peripheral sets, encryption, processing power, advanced timers and large Flash and SRAM memory.

"This series is a major addition to the STM32 platform and reinforces ST's leadership in the market for Cortex-M3 MCUs," said Michel Buffa, General Manager of ST's Microcontroller Division. "ST's proprietary 90nm process and the development of the ART Accelerator enable perfectly optimized processor-memory interactions with a performance equivalent to zero wait states, taking the performance of the Cortex-M3 core to its natural limits."

Block diagram of ST's proprietary Adaptive real-time memory (ART) Accelerator (Click on image to enlarge.)

"The ART [adaptive real-time memory] Accelerator is a pre-fetch queue and branch cache mechanism that stores the first instructions and constants of the branches, interrupt and subroutine calls. The penalty occurs the first time those events occur like for any pipelining mechanism. After that, the instructions stored in cache are pushed immediately in the pre-fetch queue upon recognition of a stored branch address. In addition, the embedded Flash is organized in 128-bit rows, allowing up to 8 (16-bit) instructions to be read per access," explains Franck Martins, ST's MCU marketing manager for South Asia.

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