Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

SMIC chooses Cadence for 65-nm reference flow

Posted: 06 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:nSilicon Realization Technology? design-for-manufacturing? low-power technology?

Global electronic design innovator, Cadence Design Systems, Inc., has just announced that Semiconductor Manufacturing International Corporation (SMIC), a large semiconductor foundry in China, has adopted Cadence Silicon Realization products for the design-for-manufacturing (DFM) and low-power technology at the center of SMIC's 65-nanometer Reference Flow 4.1. By utilizing the Cadence Encounter Digital Implementation System as the foundation, the companies worked together to produce an integrated end-to-end Silicon Realization flow for 65-nanometer system-on-chip (SoC) designs.

After thorough evaluation, SMIC chose the Cadence Silicon Realization products based on their reliable hierarchical flow for large-scale designs and superior quality of results. SMIC emphasized that the tight flow integration across functional, physical, and electrical domains ? for estimation, logic design, verification, physical implementation and in-design signoff technologies ? offered a significant increase in both designer productivity as well as ease of use, and gave an output with more deterministic results.

The Cadence Silicon Realization technology applied in the SMIC flow consists of Incisive Enterprise Simulator, Encounter RTL Compiler, Encounter Test, Encounter Conformal Low Power, Encounter Conformal Equivalence Checker, Encounter Digital Implementation System, QRC Extraction, Encounter Timing System, Encounter Power System, Litho Physical Analyzer, Litho Electrical Analyzer, Cadence CMP Predictor and Assura Physical Verification.

Senior director of design service at SMIC, Min Zhu states, "Our mutual customers can greatly benefit from the Cadence contributions to Reference Flow 4.1, which address two important challenges they face at 65 nanometers D design margins and yields." He explains, "Deploying the full end-to-end Cadence Silicon Realization flow for digital design, verification, and implementation along with our reference flow will enable our customers to work more efficiently and productively toward improving silicon quality and shrinking time to market."

Recently, Cadence also launched a new holistic approach to Silicon Realization which upgrades chip development beyond its traditional patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology. This novel approach is targeted on realizing products and technologies which deliver on the three demand of a deterministic path to silicon, namely: unified design intent, abstraction, and convergence. As a key element of the Cadence EDA360 strategy, this approach aims to ramp up productivity, predictability and profitability, at the same time minimizing the risk. For more information, please visit

Find related stories:
??-?company/industry news

Article Comments - SMIC chooses Cadence for 65-nm refer...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top