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Use RLDRAM II memory interface for FPGA

Posted: 14 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? Virtex-5? Reduced Latency DRAM?

This application note by Xilinx demonstrates how to use a Virtex-5 device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of up to 333 MHz with data transfers up to 667 Mb/s per pin.

It describes a CIO DDR RLDRAM II memory interface implemented in a Virtex-5 device. The first section describes the functionality of the RLDRAM II device. Other sections describe implementation and timing analysis details.

RLDRAM II, the second generation of RLDRAM, is a high-performance memory. It combines the performance-critical features that networking and cache applications need, such as high density (up to 288 MB), high bandwidth, and fast SRAM-like random access.

View the PDF document for more information.





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