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Reference design for multidrop JTAG multiplexer

Posted: 17 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:IEEE 1149.1? boundary scan-enabled devices? National Semiconductor? National Semiconductor?

In its most basic form the IEEE 1149.1(JTAG) standard envisions a single, one-bit serial link connecting all the boundary scan-enabled devices on a PC board. The data output of one device is connected to the data input of the next. The clock and control lines are common to all devices. All boundary scan-enabled devices are designed to support this basic architecture. This is the simplest way to connect a one-bit interface from device to device and for small, simple PC boards it is an appropriate architecture.

For PC boards with many devices this simple architecture can become unwieldy. It is often desirable to address a limited set of the devices on a PC board through the JTAG TAP. Sometimes it is necessary to address only a single device. This is frequently the case for in-system programming of programmable logic devices. Addressing only a subset of the boundary scan-enabled devices on a PC board is not possible with the most basic IEEE 1149.1 boundary scan architecture. A support device for the IEEE 1149.1 test access port that enables such addressing is required.

National Semiconductor manufactures two devices to address this requirement: the SCANSTA111 and the SCANSTA112. Both devices enable partitioning and multiplexing of IEEE 1149.1 boundary scan chains. The SCANSTA112 7-Port Multidrop IEEE 1149.1 Multiplexer provides seven local scan ports. The SCANSTA111 Multidrop Addressable IEEE 1149.1 Port provides three local scan ports. Operation of the two devices is similar.

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