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Cadence, SMIC collaborate for 54nm SoC flow

Posted: 13 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:DFM? design-for-manufacturing? reference flow? 65nm? SoC?

Cadence Design Systems Inc. reports its silicon realization technology was been chosen by Semiconductor Manufacturing International Corp. as the basis for its 65nm Reference Flow 4.1.

The companies collaborated to provide an integrated end-to-end Silicon Realization flow for 65nm SoC designs based on Cadence's Encounter Digital Implementation System. The technologies used in the SMIC flow include Incisive Enterprise Simulator, Encounter RTL Compiler, Encounter Test, Encounter Conformal Low Power, Encounter Conformal Equivalence Checker, Encounter Digital Implementation System, QRC Extraction, Encounter Timing System, Encounter Power System, Litho Physical Analyzer, Litho Electrical Analyzer, Cadence CMP Predictor and Assura Physical Verification.

Min Zhu, senior director of design service, SMIC, noted that "Our mutual customers can greatly benefit from the Cadence contributions to Reference Flow 4.1, which address two important challenges they face at 65nm -- design margins and yields." He added that "Deploying the full end-to-end Cadence Silicon Realization flow for digital design, verification, and implementation along with our reference flow will enable our customers to work more efficiently and productively toward improving silicon quality and shrinking time to market."

Cadence's new holistic approach to silicon realization moves chip development beyond the traditional patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology. This approach focuses on offering products and technologies that deliver unified design intent, abstraction, and convergence to increase productivity, predictability and profitability while reducing risk.

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