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Design methods shift to software, part 2

Posted: 24 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:IP integration? software? hardware? design?

Editor's note: This is the second of a two part opinion piece. The first part Design methods shift to software was written by James Hogan and posted on Nov. 30.

Differing from previous changes to the abstraction level of design that have occurred, block level goes down into the implementation flow and also goes up into the software development flow. Software and chip-design need to be verified against each other. Because the purpose of the chip is to run the software load, it can only be optimized this way.

Currently there is no fully-automated flow that goes all the way from the block level into implementation. A chip would typically have blocks of synthesizable IP typically in Verilog, VHDL or SystemVerilog along with appropriate scripts to create efficient implementations. Other blocks are designed at a higher level, or, perhaps pulled from the software for more efficient implementation. These blocks are in C, C++ or SystemC. The important technology here is high-level synthesis (HLS) which provides the capability to reduce system behavioral models to SoC almost automatically.

Designs like this are very difficult to verify efficiently because of the mixture of languages and accuracy. FPGAs are the medium of choice of choice for this because they can accept this mixture of languages; are fast enough to run a large verification load; and they introduce no silicon variance, already being silicon proven.

Going up from the block level creates a virtual platform. The challenge then is transitioning enough blocks so that fast hardware models exist with fidelity, for otherwise the delay and effort to do the modeling makes the software development schedule unacceptable.

Virtual platforms, and some other hardware-based approaches such as emulation, straddle a performance chasm. Software developers require performance millions of times faster than is appropriate for chip design. Of course at some level, if the technology were available, everyone would like high accuracy and high performance. We would all use Spice all the time if it ran faster than RTL but it is impossible to do that. Instead, performance is purchased by throwing away accuracy.

However, it is still necessary to be able to move up and down this stack dynamically: boot Linux at high performance (seconds not hours), and then drop to a higher level of accuracy to run a couple of frames to a display processor to check the hardware functions correctly. Run fast until just before a bug seems to occur, then drop down and investigate what is really going on. High performance or high accuracy is not good enough, both are required: the software performance model doesn't have enough accuracy to debug the system hardware and the slower models can only boot Linux on a geological timescale.

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