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Tokyo University designs NVM architecture using Docea's Aceplorer

Posted: 20 Jan 2011 ?? ?Print Version ?Bookmark and Share

Keywords:Aceplorer software? non-volatile memory architecture? resistance-change memory?

The University of Tokyo will use the Aceplorer software of Docea Power SAS to develop a non-volatile memory (NVM) architecture as part of a Japanese research project, according to the French design-for-power startup company.

The research project aims to evaluate the effectiveness of a new NVM design architecture developed by the team of Ken Takeuchi, associate professor of electrical engineering, at the University of Tokyo's Takeuchi Laboratory. The new memory, dubbed ReRAM for resistance-change memory, consumes significantly less power during data writing and shows less bit-rate failure.

"Our new NVM architecture shows significant advances in terms of speed, power consumption and reliability," commented Takeuchi. "By using Docea's Aceplorer to model power consumption at the ESL, we can investigate the optimum architecture design and share the power consumption performances with system architects."

Aceplorer is an ESL tool for modeling, simulating and analyzing the power, energy and thermal behavior of electronic systems.

The solution answers the needs of system architects in charge of power optimization of on-chip (SoCs, SiPs, FPGAs, ASICs) or on-board (embedded systems) designs. Aceplorer allows the modeling of heterogeneous systems, with any mix of digital, analog or mixed-signal blocks, and with different levels of model complexity. The result is a larger exploration of the design space for the best low-power implementation strategy, which can take into account the embedded software impact on the design power consumption, the company said.

Anne-Fran�oise Pele
EE Times

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