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32/28-nm reference flow for Common Platform Alliance ushered

Posted: 20 Jan 2011 ?? ?Print Version ?Bookmark and Share

Keywords:reference flow? Common Platform Alliance? HKMG?

Global electronic design innovator, Cadence Design Systems Inc, has introduced a qualified 32/28nm reference flow targeting Common Platform technology. Cadence worked closely with members of the Common Platform alliance (IBM, GLOBALFOUNDRIES, and Samsung Electronics) to develop a comprehensive flow from RTL synthesis to GDSII signoff for the advanced node, low-power high-k metal gate (HKMG) process technology.

This Silicon Realization reference flow for the Common Platform alliance is built around the Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System. It was validated using the 32/28nm ARM low-power physical libraries, and employs the Common Power Format (CPF)-enabled Cadence Low-Power Solution to maintain power intent throughout the design process.

The flow encompasses key foundry-validated technologies, consisting of physically aware synthesis, large-scale rapid design exploration and physical prototyping, advanced timing and signal integrity concurrent optimization with multi-mode and multi-corner analysis and optimization, context-aware placement, advanced OCV-aware clock tree synthesis, litho-aware routing, and in-design signoff analysis for timing and power. Moreover, concurrent design for manufacturing (in-design DFM) technology is permitted on demand to ensure manufacturability at 32 and 28nm. The Cadence Silicon Realization reference flow is fully optimized to deliver significant power savings with utmost quality on all counts, and offers time-to-market advantages.

The recently announced Silicon Realization flow is the latest Cadence offering supporting the EDA360 vision, which, among other things, calls for industry-wide collaboration to address the challenges of today's complex designs.

Meanwhile, the Common Platform partners unify silicon-proven tools, end-to-end flows and methodologies as an aid to advanced designers looking to achieve better predictability in design convergence, superior quality of silicon and higher design productivity.

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