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ADCs, DACs offer wireless interoperability

Posted: 24 Jan 2011 ?? ?Print Version ?Bookmark and Share

Keywords:ADCs? DACs? converters? wireless?

NXP Semiconductors N.V. reports that its Convertisseur Grande Vitesse (CGV) series of data converters are now interoperable with Nujira's OpenET envelope tracking (ET) and digital pre-distortion (DPD) solutions for 3G and 4G wireless infrastructure applications.

NXP's CGV series of JESD204A-compliant ADCs and DACs are the first in the industry to implement the JEDEC JESD204A serial interface which cuts the number of interconnect signals between data converters and VLSI logic devices, enabling synchronous bonding of multiple data converter channels or lanes. The converters have been tested for interoperability using Nujira's OpenET development system, which implements envelope tracking and DPD functionality.

Interoperability and interworking between programmable logic devices and high-speed converters is a critical acceptance criterion for equipment designers, because it reduces risk and cost associated with project schedules.

Nujira's next-generation Coolteq-h Envelope Tracking modulators now also support JESD204A as an interface option. They enable high-efficiency power amplifiers for wireless infrastructure to dynamically reduce the electrical power to a radio transmitter at times of low signal amplitude, and increase it when a powerful signal is required. Nujira's DPD technology has been developed to improve signal quality while maintaining high efficiency, which is critical for modern base stations.

The JESD204A-compliant CGV converters from NXP are suitable for cellular base stations and other wireless communication infrastructure equipment, as well as medical, instrumentation and military/aerospace applications. They also deliver a number of enhancements over and above standard implementations of JESD204A, including: enhanced transceiver rate up to 4Gbps typical; enhanced transmitter reach up to 100cm typical; enhanced features including Multi Device Synchronization (MDS) and pseudo random bit sequence (PRBS) generation for robustness validation; and assured FPGA interoperability.

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