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'Universal' memory combines DRAM's speed, flash's density

Posted: 25 Jan 2011 ?? ?Print Version ?Bookmark and Share

Keywords:double-floating-gate FET? universal memory technology? DRAM?

Researchers report that a single "universal" memory technology that unites DRAM's speed with flash memory's non-volatility and density has been developed at North Carolina University.

The new memory technology, which uses a double floating-gate FET, should enable computers to power down memories not currently being accessed, drastically cutting the energy consumed by computers of all types, from mobile and desktop computers to server farms and data centers, the researchers say.

"Memories made using our new double floating-gate structure should be about as fast as DRAM�and will need to be refreshed as often�but their densities will be about the same as flash," said EE professor Paul Franzon at NC State.

The double floating-gates use direct tunneling when storing charge to represent bits�instead of hot electron injection like flash�thus enabling operation at lower voltages. The first floating-gate in the stack is leaky, thus requiring refreshing about as often as DRAM (16ms). But by increasing the voltage its data value can be transferred to the second floating-gate, which acts more like a traditional flash memory, offering long-term non-volatile storage.

In operation, computers using the double floating-gate FETs for their main memory can operate normally until they become idle, at which time their data values can be transferred to the second gate in order to power down the memory chip. Then when the stored values need to be accessed again by the computer, the second gate quickly transfers their stored charge back to the first gate and normal operations can resume.

"We believe our new memory device will enable power-proportional computing, by allowing memory to be turned off during periods of low use without affecting performance," said Franzon.

So far the researchers have only built the gate structures in their new FET design and are currently performing cycling testing to make sure that memories stored and retrieved from the floating gates do not cause fatigue that could eventually wear out the devices. Flash, for instance, uses voltages so high during hot-carrier injection that devices can only survive about 10,000 read/write cycles. Double floating-gate FETs use lower voltages, but only cycling testing can determine whether the devices experience excessive fatigue.

If the test devices pass cycle testing, then the researchers' next step will be to fabricate real semiconductor memories out of them�a task the researchers hope to perform by next year. Also working on the project was Neil Spigna, a research assistant professor at NC State and doctoral candidates Daniel Schinke and Mihir Shiveshwarkar. Funding was provided by the National Science Foundation.

R. Colin Johnson
EE Times

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