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Altera unveils 28nm device portfolio

Posted: 28 Jan 2011 ?? ?Print Version ?Bookmark and Share

Keywords:Altera FPGA? 28nm devices? ASIC FPGA families?

Altera Corp. has unveiled its portfolio of 28nm devices: the Cyclone V and Arria V FPGA families, the recently expanded Stratix V FPGA and previously announced HardCopy V ASIC families.

The portfolio of 28nm devices provides advantages in transceiver technology, product architecture, intellectual property (IP) integration and process technology, according to the company's press release. The 28nm devices support transceiver speeds of 600Mbps-28Gbps. The company press release claims that its on-chip memories are optimized for performance and efficiency, with hard and soft memory controllers supporting application bandwidth, and meeting power and cost requirements.

The company has a range of system-level IP, such as PCI Express Gen2 x1 and x4, PCIe Gen3 x8, Interlaken, 40G/100G and 100 Gigabit Ethernet (100GbE). Moreover, Altera uses TSMC's 28nm High Performance (28HP) process technology for the Stratix V FPGAs and HardCopy V ASICs, and TSMC's 28-nm Low-Power (28LP) process technology for use in its low-cost (Cyclone V FPGAs) and midrange (Arria V FPGAs) product families. The use of 28HP process technology at the high end is critical in delivering the core and transceiver performance required by high-end applications.

The Cyclone V FPGA family suits motor control applications, displays and SDRs. According to the company press release, this product family offers 40 percent lower total power vs. the previous generation devices, with 12 transceivers operating at up 5 Gbps, hardened PCIe Gen2 x1 blocks, and hard memory controllers supporting LPDDR2, mobile DDR and DDR3 external memory.

The Arria V FPGA family targets applications requiring a balance of cost, low power and high performance, such as remote radio units, in-studio mixer and 10G/40G linecards. Like the Cyclone V family, Arria products offer 40 percent lower total power vs. previous generation devices, said the press release. The Arria V FPGA family devices include transceivers operating at up to 10Gbps, hard memory controllers supporting DDR3 external memory, and efficient systolic FIR) filters with variable-precision DSP blocks.

The Stratix V FPGA family addresses high-bandwidth applications such as advanced LTE base stations, high-end RF cards and military radar. Altera has expanded the Stratix V family's capabilities to cope with new market needs. The maximum transceiver data rates in Stratix V GX FPGAs were increased to 14.1Gbps to support emerging high-speed protocols, including 16G Fibre Channel (16GFC). Additionally, the density of the Stratix V GX FPGA was increased to 1.1 million logic elements in a monolithic die.

Compared with previous HardCopy ASIC devices, HardCopy V ASICs deliver higher performance for transceivers, I/Os and core logic, with higher levels of logic and memory integration. With these new capabilities, HardCopy V ASICs support a wider range of high-volume applications which require low power, lower unit cost, or improved single-event upset tolerance in production.

The new 28nm device portfolio will be supported by Quartus II development software. The Quartus II software's new Qsys system-level integration tool simplifies IP integration.

"Altera recognizes that every design is unique and customers are looking for solutions that deliver the right set of features and performance levels that meet their specific needs and still offer the ability to differentiate," said Vince Hu, VP of product and corporate marketing at Altera. "With its 28-nm portfolio, Altera is leveraging its ongoing investment in key areas, such as transceiver design, system-level IP, design tools, and process optimization with TSMC, to create the industry's broadest set of solutions."

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