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Tyndall scientists create n-type junctionless transistor

Posted: 04 Feb 2011 ?? ?Print Version ?Bookmark and Share

Keywords:n-type junctionless silicon FET? junctionless transistors? nanowire?

A team of scientists at Tyndall National Institute, University College Cork in Ireland has created an n-type junctionless silicon FET with a channel length of 50nm, an achievement that bolsters efforts to develop a junctionless transistor.

The junctionless transistor is based on the use of a control gate around a semiconductor nanowire. The gate can be used to modulate the resistance of the nanowire and to "squeeze" the electron channel and turn off the device. Doping is used to produce p- and n-type FETs but with the advantage over conventional FETs that there are no steep dopant gradients, nor junctions, thus promising simplified manufacturing.

The team, led by Professor Jean-Pierre Colinge, announced a p-type long-channel (about 1?m) junctionless silicon transistor with the publication of a paper in Nature Nanotechnology in February 2010. The nanowire had a cross-section of about 30nm by 10nm. The team has now made the junctionless transistor even smaller with 50nm channel length device and a cross-section of about 8nm by 12nm. In both cases the wire is separated from the gate by silicon dioxide insulator and the device was characterized using electron beam lithography on silicon-on-insulator wafers.

"The gate oxide is thick [5nm] by normal standards," said Colinge but he added that this was an advantage because it was not necessary to move to thinner insulator thicknesses or experiment with high-K gate insulators. This is another of the ways in which the junctionless transistor could offer lower manufacturing costs compared with conventional transistors.

In addition, simulations predicted that the junctionless transistor should have less short-channel effects than a transistor with junctions and that gate lengths down to 3nm should be achievable. In the latest work from Tyndall the short-channel effects are shown to be small, with the devices showing a sub-threshold slope of 60mV per decade and a drain-induced barrier lowering (DIBL) of 7mV.

"The semiconductor industry was excited by the development of the junctionless transistor as it could represent simpler manufacturing processes of transistors," said Professor Colinge. "The new smaller junctionless transistor is now 30 percent more energy-efficient and outperforms current transistors on the market. Working with my colleagues in the Theory Group at Tyndall, we had predicted that the transistor could perform on a smaller scale and I am happy to say that we were correct in our predictions."

Professor Colinge said that as a research group Tyndall would probably not try to make smaller junctionless transistors, although he was confident it could continue to scale.

In September 2010 Intel announced it had signed a three-year $1.5 million research collaboration with Tyndall that includes work on the junctionless transistor.

Peter Clarke
??EE Times





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