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Protocol analyzer eases DDR3 memory system design

Posted: 04 Feb 2011 ?? ?Print Version ?Bookmark and Share

Keywords:protocol analyzer? interposer? AMC?

Le Croy Corp. presented four protocol analysis products at DesignCon2011. First was the Kibra 380 protocol analyzer targeting DDR3. Second was the Summit T3-8 Protocol Analyzer that provides the feature set of the company's Summit T3-16 protocol analyzer at almost half the price and lower cost. The third product was a 90 Degree Server Interposer for the Summit PCIe line of Protocol Analyzers for tapping PCIe 3.0 signals that are transmitted between an add-in card and the riser card mounted in the narrow I/O compartment of 1U and 2U rack servers. The fourth product was a PCIe Advanced Mezzanine Card (AMC) Interposer to analyze data traffic between AMC mezzanine cards and their respective host systems.

Targeting DDR3
The Kibra 380 incorporates traditional waveform views and decoded state listings for comprehensive protocol analysis. Specialized trigger logic can identify over 65 JEDEC timing and command violations across all ranks and banks simultaneously. The system also offers additional views to help developers optimize physical address utilization and load leveling. It provides loss-less capture of address, command and control signals (ADD/CMD/CNTRL). By focusing on state-based capture and excluding the data signals, the system can record over one billion event samples, which is 8x more than the memory depth provided with today's logic analyzer-based solutions.

Aside from timing analysis, the Kibra generates performance metrics that are displayed for read, write and power down operations. Bus metrics are tracked per bank and per DIMM slot to provide insights into overall memory utilization. DDR3 Interposers are included to address RDIMM and UDIMM memory modules. The Kibra 380 can also address multi-channel DDR3 testing by cascading analyzers using the built-in synchronization ports.

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