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Solution speeds billion-plus gate design at 28nm

Posted: 07 Feb 2011 ?? ?Print Version ?Bookmark and Share

Keywords:28nm design? Cadence? gigahertz SoC?

Cadence Design Systems Inc. has announced that it is advancing the design of giga-gate/gigahertz SoCs with digital end-to-end flow at 28nm. Driven by the Cadence Silicon Realization approach, the new Encounter-based flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and core architecture and algorithm improvements in a unified design, implementation and verification flow, according to the press release.

The new digital 28nm flow enables designers to consider the entire chip flow holistically to drive breakthroughs in high-performance, low-power, mixed-signal, and even 3D-IC designscritical factors for mobility-based and multimedia SoCs.

The new flow, available immediately, supports Cadence's approach to Silicon Realization through its focus on design intent, abstraction, and convergence from RTL to GDSII, then through to packaging.

"28nm process technology is both a great opportunity and challenge for designers, with its power, performance and area advantages coupled with challenges such as process variation and new manufacturing effects," said Albert Li, director of design and development at Global Unichip Corp.

The new flow optimizes complex design at 28nm, providing a path for advanced SoC development to realize the cost benefits of smaller geometries. Key to the flow's performance is a unified digital design, implementation and verification based on intent, abstraction and convergence.





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