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Solutions model to latest 28-nm parasitic effects ratified

Posted: 03 Feb 2011 ?? ?Print Version ?Bookmark and Share

Keywords:Interconnect Technology Format? parasitic extraction? 28nm?

Synopsys Inc. has announced new extensions to its open source-licensed Interconnect Technology Format (ITF), which enables modeling of complex device structures and interconnect layers for parasitic extraction tools at 28nm and below process technologies.

Synopsys has collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) to define these extensions, which have been ratified by IMTAB members, including Altera, AMD, Apache Design Solutions, Globalfoundries, LSI, Magma Design Automation, Nvidia, Qualcomm, STMicroelectronics and Synopsys.

The ITF has been licensed by over 25 semiconductor companies and several EDA vendors since its open source availability in June of 2010. The ITF format can be licensed at no charge through Synopsys' Technology Access Program (TAP-in).

The new IMTAB ratified extensions to ITF consist of: Device conductor layer type specification to define a conductor's function based on the geometric characteristics; high-k gate oxide thickness and dielectric constant specification for accurate capacitance calculation; two-dimensional table to model rectangular via etch as a function of length and width; area-dependent temperature coefficient table for accurate via resistance calculation; model format to describe through-silicon via (TSV) for on-chip extraction to support three-dimensional IC and silicon interposer design methodologies.

The next scheduled IMTAB meeting is scheduled on March 23, 2011. The agenda focuses on 20nm modeling.

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