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PCB designers lay out FPGA challenges at DesignCon

Posted: 09 Feb 2011 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA-based PCBs? BGA pinouts? multiple domains PCB? FPGA timing?

A panel discussion at the recently held DesignCon in Santa Clara, California had designers seriously deliberating on the challenges of FPGA-based PCBs. The sad realization: the PCB designer always takes the blame for poorly designed FPGA-based PCBs.

FPGA usage has grown significantly over the past decade. As the usage has grown steadily, so have the problems of designing FPGA-based PCBs. FPGAs portend a unique challenge to PCB and system designers by offering configurable pins. The design team faces the unique challenge of optimizing the FPGA design across multiple domains PCB, schematics and FPGA timing.

HP's R&D PCB Engineer John Hutton saw the challenge in what is perhaps an FPGA's best advantage, that of being programmable: "FPGAs are too darn flexible." He complained that FPGAs cause routing issues in that they do not enforce following rules in the use of pins. "What we need is an automated routing/breakout/pinout right-time-first methodology."

Cisco's PCB designer Darren Hopcroft echoed those sentiments: "Assigning the appropriate pinouts is a challenge to keep the routing on the PCB board effective."

The lone FPGA vendor representative on the panel offered this thought about not assigning standard pinouts in FPGAs to be used on a board. "BGA pinouts are not standardized because the feedback from PC designers is too restricted," said Andy DeBaets, senior director of systems and applications engineering at Xilinx. A typical 416-page document called "Virtex-5 FPGA Packaging and Pinout Specification" gives an idea on the choices for pinouts and iterations in changes to pinouts faced by the PC designer.

DeBaets suggested that PCB designers send the early FPGA RTL design through common implementation tools to validate the design. "This way there is minimum disruption in routing problems down the road at the end of the design," said DeBaets. He suggested such an implementation tool as Cadence's Allegro system planner does a good job predicting design constraints.

Panelist Nagesh Gupta, engineering group director at Cadence Design Systems, elaborated: "FPGAs in competing requirements for different tools. Changes are costly when done manually. What's more, the later the changes, the more it is going to cost you."

InPA Systems' vice president of marketing and business development Joe Gianelli suggested that "a diagnostic bus be designed into the system. "InPA has patent-pending "active debug" technology which provides visibility to detect hardware faults, and reduce the FPGA place and route iterations. The startup exhibited its technology at DesignCon after coming out of stealth mode last year.

- Nicolas Mokhoff
??EE Times





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