Tensilica allows customer evaluation of Atlas DPUs

Tensilica recently announced that customers may now evaluate the optimized programmable dataplane processing units of its Atlas Reference Architecture. Atlas complies with the 3rd Generation Partnership Project (3GPP) Long-Term Evolution (LTE) standard, and other complementary standards including Evolved High-Speed Packet Access (HSPA+) and WiMAX.

The Atlas Reference Architecture uses the Tensilica ConnX BBE16 baseband DSP core coupled with three function-specific dataplane processor cores to allow baseband PHY SoC developers to create a low-power and minimal-size PHY system, while enjoying the flexibility of a fully programmable radio, which is needed for competitive multistandard user equipment devices and femtocells.

The ConnX BBE16, introduced in February 2010, is the single DSP part of the Atlas reference architecture, as it is built around a core vector pipeline made of sixteen 18bx18b multiply accumulators. ConnX BBE16 is optimized for performance of DSP kernel operations such as fast Fourier transform and Finite Impulse Response as well as matrix multiplies.

There are several other functions that must be implemented for a fully functional PHY system, and these are better implemented in function-specific DPUs to offer lower power and smaller size, and address the control functions required.

The three other Atlas components are:

???The ConnX Soft Stream Processor (ConnX SSP16), a 16-way SIMD (single instruction, multiple data) baseband core optimized for the processing of soft bits, used for the acceleration of wireless communication PHY routines such as Viterbi, HARQ, and de-rate matching, as well as data manipulation and movement operations
???The ConnX Bit Stream Processor (ConnX BSP3), a baseband core optimized for the processing and control of bit streams, used for the acceleration of wireless communication PHY routines such as bit mapping, bit interleaving and turbo encoding
???The multistandard ConnX Turbo Decoder (ConnX Turbo16), a programmable turbo decoder for LTE and HSPA+ that achieves 150Mbit/s decoded bit rate for LTE. The size of this multistandard turbo decoder is in line with most RTL hardware implementations in terms of power and area.

The ConnX SSP16 and ConnX BSP3 DPUs are available for evaluation now. The multistandard ConnX Turbo16 DPU will be available for evaluation June 2011.

Tensilica has also launched the ConnX BBE64-128 DSP intellectual property cores for SoC design. It provides over 100GigaMACs performance in 28nm high-performance process technology.

- Colin Holland
??EE Times