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HSIC-compatible PHY IP delivers power, area savings

Posted: 17 Feb 2011 ?? ?Print Version ?Bookmark and Share

Keywords:high-speed inter-chip? HSIC-compatible PHY IP? SuperSpeed USB 3.0? USB 2.0 IP?


Evatronix SA recently released a high-speed inter-chip or HSIC-compatible PHY IP that delivers considerable power and area savings in USB 2.0 chip-to-chip connections. The company develops USB-IF certified solutions for SuperSpeed USB 3.0 and USB 2.0 IP.

The HSIC technology enables users to set up a direct connection on a PCB between a USB host chip and other on-board USB devices. The HSIC standard promises much less power consumption by eliminating the requirements to support long external USB cables while remaining USB protocol-compliant and USB software-compatible.

Through a 240MHz DDR interface, the HSIC standard provides full support for the 480Mbit/s data transfer of the USB protocol. It eliminates 3.3 and 5V signaling, enabling significant silicon area and power savings in comparison to standard cable USB 2.0 PHYs. Evatronix's USBHSIC-PHY logic macro is now available on the LFoundry 150nm process and can be ported to any technology node from 65nm to 180nm.

Julien Happich
EE Times

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