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Toshiba develops power-saving flip-flop circuit

Posted: 23 Feb 2011 ?? ?Print Version ?Bookmark and Share

Keywords:flip-flop circuit? digital SoC? clock buffer?

Toshiba Corp. recently announced that it has created a new flip-flop circuit. Developed in a 40nm CMOS process, the circuit reduces power consumption in mobile devices.

"Measured data verifies that the power dissipation of the new flip-flop is up to 77 percent less than that of a typical conventional flip-flop and that it achieves a 24-percent reduction in total power consumption when applied to a WLAN chip," Toshiba said.

A flip-flop is a circuit that temporarily stores one bit of data during arithmetic processing by a digital SoC incorporated in mobile equipment and other digital equipment. As a typical SoC uses 100,000 to 10 million flip-flops they are an essential part of SoC design.

A typical flip-flop incorporates a clock buffer to produce a clock inverted signal required for the circuit's operation. In order to save power, Toshiba changed the structure of the typical flip-flop and eliminated the power-consuming clock buffer.

Toshiba will describe the flip-flop at the 2011 IEEE International Solid-State Circuits Conference (ISSCC).

- Mark LaPedus
??EE Times

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