Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Controls/MCUs

Intel bares technical details of Sandy Bridge

Posted: 25 Feb 2011 ?? ?Print Version ?Bookmark and Share

Keywords:Sandy Bridge? modular ring interconnect? debug bus?

Intel Corp. has used the International Solid-State Circuits Conference (ISSCC) to reveal further technical details of its 32nm Sandy Bridge processor. In a presentation made on February 22, the company thoroughly described the processor's modular ring interconnect, the design techniques used to minimize the cache's operational voltage and the inclusion of a debug bus for monitoring traffic on the interconnect.

The 32nm Sandy Bridge processor integrates up to four x86 cores, an optimized GPU, and DDR3 memory and PCI Express controllers on the same die, according to the paper presented at ISSCC by Ernest Knoll, a designer at Intel's design center in Haifa, Israel. Sandy Bridge features 1.16 billion transistors and a die size of 216sq mm, Knoll said.

The Sandy Bridge IA core implements several improvements that boost performance without increasing power consumption, including an improved branch prediction algorithm, a micro-operation cache and a floating point advanced vector extension, according to the paper. The devices' CPUs and GPU also share the same 8MB level-3 cache memory, as stated in the paper.

Although the L3 cache units are organized in four slices along with the x86 cores, 2MB per core, they are fully shared with the GPU, Knoll added.

Sandy Bridge's ring interconnect fabric connects all the elements of the chip, including the CPUs, the GPU, the L3 cache and the system agent. Because the ring interconnect is modular, the four-core die can easily be converted into a two-core die by "chopping" out two cores and two L3 cache modules, according to Knoll's presentation. The initial version of Sandy Bridge is available in two- or four-core variations.

"By simply 'chopping' two slices, we get to another level of die," Knoll said.

Intel provided the first details about the Sandy Bridge family of heterogeneous processors at the Intel Developer Forum last September. Intel introduced the first Sandy Bridge products, the second generation of the company's Core processor family, at the Consumer Electronics Show in January. Some of the devices have been shipping since early January and Intel expects them to be incorporated into more than 500 laptop and desktop PC designs this year.

1???2?Next Page?Last Page

Article Comments - Intel bares technical details of San...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top