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DesignWare IP supports PCIe 3.0 specification

Posted: 03 Mar 2011 ?? ?Print Version ?Bookmark and Share

Keywords:digital controller? dma engine? 256-bit datapath?

Synopsis Inc. has enhanced its DesignWare digital controllers to support the PCI Express 3.0 specification recently released by PCI Special Interest Group. The digital controllers now include features such as support for PIPE 3.0 specification (v.09), PCI-SIG Engineering Change Notifications (ECNs), 256-bit datapath and embedded DMA engine to improve the performance of the PCIe interface.

The DesignWare IP for PCIe 3.0 (Gen 3) is currently used by semiconductor companies developing high-performance enterprise computing SoC designs. The DesignWare portfolio of silicon-proven digital controllers for PCI Express 3.0 includes Endpoint, Root Complex, Switch and Dual Mode cores, enabling designers to integrate the 8.0 GT/s PCI Express 3.0 interface into their SoC designs.

The optional ECN's supported by the DesignWare digital controllers enable power reduction and increase performance for specific applications. Supported ECNs include TLP Processing Hints, ID Based Ordering, Atomic Operations, BAR Resizing, Extended TAGs, Latency Tolerance Reporting and Optimized Buffer Flush/Fill.

The 256-bit datapath targets SoCs for the enterprise computing market that require a 16 lane (x16) PCIe 3.0 interface. The DesignWare digital controllers with 256-bit datapath are designed to handle multiple packets arriving in a single clock cycle.

The embedded DMA engine offloads the main SoC processor when moving large amounts of data between the PCIe interface and the rest of the system. It supports the native application interface or ARM AMBA AHB and AXI3 bridges while also supporting advanced features such as multiple channels, interleaving, linked list and full duplex operation.

The DesignWare IP for PCI Express 3.0 is now available. It will be demonstrated at the IP Summit at SNUG San Jose, March 30 at the Santa Clara Convention Center.

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