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3D TSVs get boost from IMEC, Microtech

Posted: 09 Mar 2011 ?? ?Print Version ?Bookmark and Share

Keywords:3D? TSV? IC? test? probe?

Cascade Microtech Inc. and IMEC have embarked on a collaborative research partnership for testing and characterization of 3D IC test structures. The two organizations will work together to develop test methods and methodologies for emerging 3D-Through-Silicon-Via (TSV) structures. They will also work for the drafting of global standards for 3D IC development and production test.

Demand for tablet PCs and smart phones is driving processor vendors to use 3D-TSV techniques to stack memory on processors to achieve higher performance without the need for node shrinks. The emerging 3D-TSV technology allows multiple chips to be stacked and integrated into one small form factor using less power offering increased bandwidth of interchip communication by eliminating connections through the circuit board.

Chip stacking with 3D-TSV interconnects requires Known-Good-Die (KGD) wafer probing with high test coverage before stacking in order to achieve practical stack yields. The high density of TSV interconnects has challenged conventional probe card architectures thus limiting electrical test access.

The complexities of test inherent in new 3D-TSV IC designs will be a key focus of the research project that will take place at IMEC's research facilities in Belgium, where silicon wafers with test probe structures of 40 micron pitch and smaller will be manufactured and tested. In the process of ongoing research, IMEC will install the first turnkey 3D test solution comprising of a 3D-TSV probe station and a new probe card from Cascade Microtech. The probe station and probe cards will be used to characterize the TSVs in the chip stacks as part of ongoing efforts to optimize 3D stacked IC performance and reliability.

Erik Jan Marinissen, principal scientist, IMEC, explains that "The collaboration with Cascade Microtech in this early phase of engineering and development will enable us to identify challenges and provide solutions for test issues that are specific for 3D integrated systems. Enabling probing solutions for high-density interfaces, minimizing the impact of pre-bond testing on stacking yield and test access to buried layers are key challenges for testing 3D systems that we will address through this collaboration."

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