Flip chip packaging boasts 40% lower cost

STATS ChipPAC has released a flip chip packaging technology, fcCUBE, that features copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and enhanced assembly process. The technology boasts high input/output (I/O) density, high performance and reliability in advanced silicon nodes. The fcCuBE technology offers enhanced flip chip packaging with a 20-40% lower cost over standard packaging.

Package structure, design and assembly are key to high performance, cost effective solutions as semiconductor devices are scaled to wafer technology nodes of 45/40nm and below. The fcCUBE technology delivers benefits such as scalability to very fine bump pitches of 80 micron and below with finer effective pitches. The packaging technology has high resistance to electromigration phenomenon which can result from the higher current density induced by the scaling of features. It is also a lead-free alternative to conventional solder-based bumps.

"The compatibility of fcCuBE technology with advanced silicon nodes has been proven down to 45/40nm, and early testing at the 28nm silicon node have shown equally promising results," said Dr. Han Byung Joon, EVP and CTO of STATS ChipPAC. "We are seamlessly deploying the core fcCuBE technology beyond traditional single-die flip chip packaging into more complex stacked/3D packages including Package-on-Package (PoP), Package-in-Package (PiP), flip chip/wire bond hybrid packages and next-generation Through Silicon Via (TSV) configurations."

The fcCuBE technology is based on STATS ChipPAC's BOL interconnect structure combined with Cu column bump. Although copper is a harder bump material that can cause damage to Ultra low-k (ELK/ULK) layers in finer silicon nodes, the fcCuBE interconnect structure provides an effective solution to the challenges in the semiconductor industry. STATS ChipPAC has completed extensive thermo-mechanical simulation testing on fcCuBE technology with results demonstrating a significant reduction of stress on ELK/ULK structures which are consistent with empirical data generated with 45/40nm as well as 28nm node product test vehicles.