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Memory controller IP enables timing closure, higher yield

Posted: 25 Mar 2011 ?? ?Print Version ?Bookmark and Share

Keywords:Self-Calibrating Logic? memory controller IP? timing closure?

Timing closure remains one of the most daunting tasks facing memory controller design. Using the conventional method for chips produced at 40nm and below, designers must implement multiple clock delay lines within the PHY then test the first hundred engineering samples to permanently set the clock read delay for optimal yield.

Semiconductor IP innovator Uniquify has developed "Self-Calibrating Logic (SCL)," a patented solution in which the memory controller does a self-test on every power-up to select the optimal delay. In the case of ASIC/ASSP/SoC designs, the result is higher yield, even if the foundry process drifts.

Today's deep sub?m SoC designs integrate DDR memory controllers that operate at multiGHz clock rates. At these clock rates, system-level memory read-write timing margins are measured in picoseconds. Designing DDR PHYs that satisfy these timing requirements can require exhaustive rounds of incremental IC design modifications, and the resulting silicon often fails to produce high-yielding devices in high-volume production.

Uniquify's memory controller IP, which incorporates its patented SCL technology, performs a system self-test on power-up that allows the controller's PHY circuitry to automatically fine-tune timing parameters every time the host SoC is reset. Not only does SCL eliminate the need for excessive design tweaks to achieve timing closure during the SoC development stage, chips with SCL are much higher-yielding due to their ability to automatically adapt their timing characteristics for a wide range of system-level design choices and for variations in the SoC foundry process.

"System level timing requirements are the most challenging part of memory controller design. Precise details about the system board design, the type of external memory devices used, and even details about the host SoC may not be finalizedor may not be well characterizedwhen the DDR PHY is initially designed," explained Uniquify CEO and founder Josh Lee. "Our patented SCL technology allows Uniquify to move the final determination of exact timing parameters from the IC design stage to system power-on in the field, when all of the characteristics that affect timing are finalized and implemented."

Conventional approach too rigid
The conventional approach to managing critical timing requirements is for chip designers to measure the actual timing characteristics on the first several hundred SoC engineering samples, and then manually set timing parameters using programmable on-chip registers. Permanently setting timing parameters after only a few hundred samples have been fabbed, however, has proven problematic for deep sub?m designs.

"At current process nodes, even minor variations in the foundry process can cause timing parameters to drift, which will produce significant yield loss in volume production," said Uniquify DDR solutions architect Mahesh Gopalan. "SCL automatically accommodates normal process variationwithout yield lossby continuously modifying timing parameters at every power-up. Even system-level aging, which can alter board-level trace delays over years of use, can be accommodated by SCL, thereby improving overall system reliability."

Uniquify uses SCL technology in the PHY part of its memory controller IP. The company's DDR1, DDR2, DDR3 and DDR2/3 Combo IPs have been licensed to companies worldwide.

- Clive Maxfield
??EE Times

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