IP core requires no off chip DRAM

The CFS is a patent-pending technology whose main features include high compression of the reference frame store, depending on the desired quality. Its bitstream is also fully compatible with existing, third-party decoders with no error drift. The technology is not restricted to the H.264 standard and could be potentially applied to other video compression algorithms.

The CFS technology makes a highly compressed reference frame store practical that can result in the integration of the CFS memory in a SoC and the elimination of the external DRAM. This results in a substantial reduction in the power requirements. CFS size can be smaller than 1Mbit for 720p or ~2.2 Mbits for 1080p.

The company believes that this technology will enable a new class of low power H.264锟絛evices for锟絚onsumer products such as camcorders, cameras, mobile phones as well as embedded applications in video surveillance and automotive.

The H.264 CFS Encoder is working in an Avnet FPGA board encoding 720p@30 video using a Xilinx Virtex-5 part as a technology readiness demonstration.

The size of the H.264 CFS encoder is approximately 280kgates + 217 Kbits of single and dual port memories + CFS memory for a fast 130 nm process, at 250MHz (1080p@30), worst case process, low voltage, worst case temperature (125°C).

The H.264 CFS Encoder IP core is immediately available as VHDL or Verilog source or FPGA netlist. The H.264 limited decoder will be available in Q2.

The design is fully synchronous, single clocked soft IP core. Only the rising edge of the clock is used and there are no transparent latches.

Customers wishing to evaluate the IP can request the bit accurate C model and the User's Guide. Selected customers can have access to a timed FPGA netlist.