Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Cadence introduces wide I/O IP

Posted: 05 Apr 2011 ?? ?Print Version ?Bookmark and Share

Keywords:I/O IP? memory controller? power?

Cadence Design Systems Inc. has announced their release of a licensable, wide I/O memory controller core, which they claim is the first in the market.

''The Cadence wide I/O interface goes beyond the proposed low-power metrics of the standard, offering additional power-saving features such as 'traffic sensing,' which automatically adjusts the power consumption based on the type of traffic,'' according to the EDA house. ''The IP has been designed to support operation at multiple frequencies, and allows designers to implement advanced power-control techniques, such as dynamic voltage and frequency scaling (DVFS), to reduce power even further," according to Cadence.

Wide I/O, a memory interface standard in review at JEDEC, defines a 512bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8 gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions.

The wide I/O interface allows a large array of low-cost and low-power connections between an application processor and the DRAM stacked on top of it. The result is a system that can achieve higher bandwidth with less power while also meeting the goals of reduced PCB area and component height. As a result, it is critical that designers also have access to advanced 3D IC assembly and design methodologies.

The Cadence 3D IC platform includes advanced capabilities, such as support for through-silicon vias (TSV), to enable the use of vertical electrical connections for significantly reduced board space, cost and power.

For years, chip makers have been talking about 3-D chips based on TSVs. But except for select productssuch as CMOS image sensorsthe technology has not moved into the mainstream, due to costs, lack of standards and other factors.

Now, chip makers may have identified a new device vehicle that could propel TSV-based 3-D chips into the mainstream: a wide I/O DRAM for cellphones and related products. One group is seeking to accelerate this technology into the marketplace. Recently, Sematech, SIA, and SRC announced a program to drive industry standardization and the technical specifications for heterogeneous 3-D integration.

The Cadence wide I/O memory controller is available now.





Article Comments - Cadence introduces wide I/O IP
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top