Memory controller claims first DDR4 IP solution

Cadence Design Systems Inc. has introduced a DDR4 solution that it says will enable SoC designers to take advantage of the performance gains of the emerging DDR4 memory standard. Having worked with hundreds of customers to integrate earlier generations of this important memory controller interface, Cadence and the newly acquired Denali team boast a proven, high-quality IP and sophisticated integration environment required to speed integration, reduce cost and ensure design manufacturability. The solution includes hard and soft PHY IP; controller IP; memory models; verification IP; tools and methodologies; and signal integrity reference designs for the package and board.

The DDR4 specification, an evolutionary SDRAM memory technology standard currently under review at JEDEC, proposes speeds ranging from 1600 mega transfers per second (MT/s) up to 3200 MT/s, more than 50 percent faster than the current DDR3 standard. As the standard evolves to support higher frequencies and throughput, signal integrity, power and performance issues multiply. Successful IP integration hinges on both the quality of the IP and the sophistication of the integration environment. The Cadence integration environment aims to enable customers to model and analyze their target memory topology, and verify the behavior of the IP at both the SoC and system levels.

The soft PHY and controller provide flexibility and can be synthesized to support the full range of frequencies and voltages. Designers can deliver either a pure DDR4 SoC, or combine DDR4 with other technologies like DDR3 or LPDDR2. The specification is expected to be finalised this year.

DDR4 controller IP, verification IP and memory models are available now, and supported by both Cadence and third party design tools and methodologies. A soft DDR4 PHY is expected to be available this quarter, while a hard PHY solution for 28nm TSMC geometries is expected to be available by Q3 2011.