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Intel-Micron duo drives NAND to next node

Posted: 19 Apr 2011 ?? ?Print Version ?Bookmark and Share

Keywords:Intel-Micron? 20nm NAND process? 8GB NAND flash? multilevel cell technology?

Flash memory has a limited number of program-erase (P/E) cycles. Older NAND products are said to withstand around 100,000 P/E cycles. Then, wear begins to deteriorate the reliability of the device. To drive down costs, many OEMs have migrated to 50nm-class devices, based on MLC technology. These types of devices, equipped with 4bit error correction, have 10,000 endurance cycles.

Now, OEMs are looking at 30nm-class NAND and below, based on MLC. These types of devices, equipped with 8bit error correction, have only 5,000 endurance cycles.

Intel and Micron said that the 20nm device will enable 5,000 endurance cycles. That could still be suitable for USB drives, SSDs and most other applications. Right now, 5,000 endurance cycles ''is good,'' Handy said. ''Plus, the sooner IMFT reaches 5K the harder it will be on competitors who ship anything less.''

''That's impressive,'' added Gregory Wong, an analyst with Forward Insights, but ''the ECC requirements are likely higher.''

How to make 20nm NAND
For years, Intel and Micron have had a successful NAND manufacturing venture called IM Flash Technologies. The venture has one 300mm fab in Lehi, Utah, which is producing 25nm NAND devices. Both Intel and Micron share the output.

Initially, the 20nm process is being ramped up in IM Flash Technologies' fab in Lehi. ''Lehi is our lead fab,'' said Kevin Kilbuck, director of marketing for Micron's NAND Solutions Group, in a conference call.

The Intel-Micron duoand other NAND playershas defied the laws of physics. In theory, today's 193nm immersion scanners will hit the wall around 20nm or so. IM Flash and others have been able to devise 25nm-class NAND chips with today's 193nm immersion lithography, plus self-aligned double-patterning (SADP) techniques, observers speculated. It is widely believed that IM Flash is using scanners from ASML Holdings NV and SADP technology, observers speculated.

The Intel-Micron 20nm process is ''pretty impressive. They pushed the limits of DPT to obtain a shrink of around 30 percent,'' said Wong of Forward Insights, referring to double patterning technology. For years, NAND flash vendors have used double patterning, it was noted.

Intel and Micron declined to comment on the manufacturing techniques used in the 20nm process. For 20nm, the venture is using ''existing tooling,'' said Troy Winslow, director of product marketing for Intel's Non-Volatile Memory Solutions Group.

The joint venture has begun producing limited NAND wafers at its new 300mm fab venture in Singapore, but the company is missing an important piece of the puzzle: Intel. As reported, the chip giant has yet to invest in the Singapore fab. Micron and Intel insist they have a strong relationship.

The Singapore fab is not ramping up 20nm processes. It is ramping up 25nm NAND. Next week, IM Flash Technologies in Singapore will have a grand opening, according to Micron.

- Mark LaPedus
??EE Times

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