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IMEC bares new bulk FinFET fabrication process

Posted: 25 Apr 2011 ?? ?Print Version ?Bookmark and Share

Keywords:bulk finFET? finFET fabrication? plasma-free? dry oxide removal? planar CMOS?

IMEC has discovered and introduced a new and improved process flow to fabricate bulk finFETs using a plasma-free dry oxide removal process.

IMEC presented the new process flow during the 2011 Ultimate Integration on Silicon (ULIS) Conference held in Ireland last March. It showed significant advancements in critical FinFET fabrication steps integrated in a tri-gate FinFET flow to make 20nm wide fins in pitches ranging from 200nm down to 90nm.

FinFETs, obtained with this new integration scheme, and co-integrated with planar CMOS in the same wafer, showed good morphological and electrical characteristics.

Bulk FinFETs are key devices for advanced technology node applications, such as analog circuits and SRAMs because of a very good short channel effect control and transistor compactness.

Up to now, fin height control and recess of shallow trench isolation (STI) oxide were still critical challenges in the integration of FinFETs.

FinFET fabrication

Figure 1: HF-based field recess shows oxide footing because the sidewall is covered by thermal oxide which etches slower than the field oxide (A). Siconi results in reduced footing because this etching technique is less sensitive to oxide density (B).

FinFET planar

Figure 2: (Left) tilted top scanning electron microscopy (SEM) showing planar and FinFET regions after gate patterning and (right) corresponding Id/Vg curves.

IMEC's new process has been demonstrated in a 65 nanometer technology node FET/FinFET co-fabrication flow. The process flow for co-integration uses two oxide field recess steps to finally achieve the target topographies for FinFETs and planar FETs (50nm for FinFETs and flat for planar FETs).

IMEC reported that morphological and electrical results indicated well-filled trenches, better fin height control and bulk FinFET static performance similar to planar CMOS. The availability of such a FET/FinFET co-fabrication flow is attractive for integration of planar CMOS circuits with SRAMs.

Improvements in these critical fabrication steps were obtained by adopting the Siconi

Selective Material Removal (SMR) chamber of applied materials in the fabrication flow which results in the ability to selectively remove silicon oxide in a controlled (digital) manner.

The new dry oxide removal process is applied after trench etching (using a carbon/nitride double hard mask approach) and STI trench fill with oxide.

In a sequence of steps, a well-controlled amount of oxide (20nm) is consumed in each step, giving a digital character to the etch process.

Next, nitride is removed in a hot phosphoric bath and finally the oxide field is recessed until the desired level of fin height is attained.

This fin formation method is more robust than conventional wet oxide etch as it has little dependence on the local oxide density variation. In addition, using a wet etch process has the undesirable characteristic of leaving an oxide foot on the fin sidewall and of opening voids in the oxide fill material.

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