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Manufacturing/Packaging??

Packaging tool offers advanced miniaturization

Posted: 28 Apr 2011 ?? ?Print Version ?Bookmark and Share

Keywords:packaging? miniaturization? chip design?

Cadence Design Systems Inc. unveiled the latest version of its Allegro PCB and IC packaging technology, offering capabilities that increase both productivity and predictability across silicon, SoC and system development. New technologies include advanced miniaturization capabilities, uniquely integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design features, and flexible team-design enablement to address global designer productivity. The company also announced that the Allegro 16.5 technology will be available through product configuration that enables users to access advanced features on-demand for specific design tasks, to optimize total cost-of-ownership.

The Allegro 16.5 features and capabilities are aimed at easing the path to co-design and analysis between engineers involved in Silicon, SoC, and System Realization, and enabling more predictable and efficient design flows that deliver higher-quality end products.

The Allegro 16.5 release provides many capabilities that enable a productive, predictable path and closure to product creation. This version has a constraint-driven flow for embedded components that employs advanced miniaturization techniques used in state-of-the-art productssuch as smart phones, tablet PCs and avionicsto reach new levels of functional density. Traditionally, manual layout is used to place and route embedded components, but this is an error-prone process with multiple iterations and no design rule checking. The Allegro technology offers a simpler way to place and route these components with its constraint-driven approach. The Allegro Power Delivery Network Analysis is integrated with Allegro PCB Editor for comprehensive power tradeoffs of fully routed PCBs.

Increasing use of standards-based interfaces such as DDR4 and PCI Express 3.0 is making timing closure on PCBs extremely challenging. The new PCB Interconnect Design Planning option uses a Cadence-patented hierarchical abstraction, coupled with semi-automatic approaches, that leverages feedback from the route engine to accelerate the path to timing closure.

The concurrent team design authoring capability of Allegro also shortens the time it takes to create design intent by leveraging the power and skill of a distributed engineering team.

Starting with Allegro 16.5, Cadence will extend SoC Realization by providing package-board-aware SoC IP. With this release, a package-board-aware DDR3 SoC IP methodology kit will be available to provide a compliant and fast implementation path from silicon IP to package and board. Similar support for other protocols, such as the recently announced DDR4 memory standard, will come in the future, according to Cadence.

Allegro technology is built upon a silicon-package-board co-design approach, with direct bi-directional integration with flows from the Cadence Encounter Digital Implementation System and Virtuoso custom analog products lines, including low-power, mixed-signal, gigahertz, RF, and SiP/3D-IC flows. Allegro products offers a scalable PCB and IC package design solution that leverages a constraint- and rules- driven methodology, from logical design authoring through physical implementation to signal and power integrity analysis and signoff.

Extending Silicon Realization, the new system-in-package (SiP) distributed co-design capability works with Encounter Digital Implementation System and Virtuoso custom analog technology to enable cross geographic, company and team design, reducing time to package-optimized chip tapeout.





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