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IP core boasts up to 10Gbps video over IP

Posted: 02 May 2011 ?? ?Print Version ?Bookmark and Share

Keywords:video processor? design platform? IP core?

Xilinx, Inc. releases Broadcast Real-Time Video Engine Targeted Design Platform and the SMPTE2022 IP core, offering acceleration of hardware development to process high quality video and deliver it at rates as high as 10Gbps over Internet Protocol. Using the Virtex-6 or Spartan-6 FPGA Broadcast Connectivity Kits as a base from which video pipeline algorithms can be created after utilising the connectivity of the kit to bring video into the FPGA, Xilinx's Broadcast offerings enables the continuous improvement of video quality while meeting the significant challenges of feeding uncompressed HD, 3D and 4K video streams over IP networks.

The Real-Time Video Engine Targeted Design Platform consists of a broadcast-quality Video and Image Processing IP pack, as well as reference designs supporting the Virtex-6 FPGA and Spartan-6 FPGA Broadcast Connectivity Kits, which include Xilinx ISE Design Suite embedded development software. The combination of IP cores, tools and hardware offers designers easy development of a real-time video processing chain for many types of broadcast applications that support various SD/HD/3D formats, frame rates and resolutions. The kits' FMC (FPGA mezzanine card) connectors allow designers to quickly evaluate and integrate SD/HD/3G-SDI, AES3 audio, DVI, HDMI, DisplayPort, 10GbE (10 Gigabit Ethernet) for video over IP, and other interfaces into broadcast designs needing real-time performance, such as for breaking news, live events and sports coverage. Applications needing the highest video quality and highest bandwidth in digital cinema and Super Hi-Vision (or Ultra HDTV) systems can also be built.

The growing adoption of 3DTV will double the bandwidth requirements as compared to 1080p60 formats, subsequently increasing the number of SDI ports required in each system implementation or increasing the speed of these ports to 6Gbps and upwards. The Xilinx Broadcast Real-Time Video Engine Targeted Design Platform accommodates today's triple-rate SDI- (SD/HD/3G-SDI) applications and accommodate the higher speeds required for Super Hi-Vision. Proposed standards such as dual 3G-SDI over 6Gbps fiber, 10G-SDI as well as others on the industry roadmap, can also be supported.

Top-tier systems developers use FPGAs for both video algorithm development as well as transporting multiple channels of HD video across IP networks in either LAN (within the studio or stadium) or WAN (between cities and from stadium to studio) environments. FPGA-based implementations of integrating systems and processing on a single chip are superior to hard-cast silicon solutions such as ASICs or ASSPs because they require shorter development time while enabling developers to continually improve video quality. FPGAs also make bridging between ever-changing standards in both the broadcast and communications industries easier while providing high reliability quality-of-service transport of video over networks, and enabling the transport of the highest quality video over multiple streams.

Key elements of Xilinx's Broadcast Real-Time Video Engine Targeted Design Platform include: 1) Video and Image Processing IP pack supporting 1080p60, 2K and 4K video processing, providing the capability to do scaling, deinterlacing, on-screen display, noise reduction and more at broadcast quality; 2) Implementation of the SMPTE2022 IP core showing full bandwidth, low-jitter 3x 3G-SDI (or 6x HD-SDI) over 10Gb Ethernet in full duplex running on the Virtex-6 FPGA Broadcast Connectivity Kit. This enables the delivery of up to six HD camera feeds uncompressed over a single link over virtually any distance; 3) The Inrevium Spartan-6 FPGA Broadcast Connectivity Kit from Tokyo Electron Devices supporting low cost FMCs for SD/HD/3G-SDI and AES3 audio and optional FMCs for various display interfaces like HDMI, DisplayPort, and V-by-One HS; 4) Virtex-7 HT FPGA 28Gbps solution highlighting the jitter performance of Xilinx's transceivers and supporting huge amounts of aggregate bandwidth for communications and broadcast backhaul links, such as for EdgeQAM/CMTS applications in cable, also targeted for supporting the 10G-SDI standard and emerging standards to handle 4Kx2K digital cinema and Super Hi-Vision 8Kx4K bandwidths; 5) Alliance Member Vanguard Software Solutions' H.264/AVC-I Video Encoder implementation showing how designers can reduce bandwidth and storage requirements without sacrificing video quality. Designers can integrate the AllianceCORE IP core into contribution, acquisition and archival systems and support SMPTE AVC-IClass50 & Class100, with High10 and High422 intra profiles; and 6) Kintex-7 family, a 28nm FPGA designed for broadcast applications with transceivers capable of supporting up to 12.5Gbps and offering twice the performance at less than 50 percent the power of previous generation FPGAs.

The Xilinx Video and Imaging Processing IP pack is priced at $3,000 and is available as of end of April. It includes multiple video and image processing LogiCore IP cores that provide a Video Processing and Image Processing capability. The Xilinx SMPTE2022 IP core will be available in Q4 2011.

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