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ITRS chairman: Tunnel FET possible transistor option

Posted: 03 May 2011 ?? ?Print Version ?Bookmark and Share

Keywords:field effect transistor? tunnel FET? power consumption?

Paolo Gargini, Intel fellow and chairman of the International Technology Roadmap for Semiconductors (ITRS) discussed at the Industry Strategy Symposium Europe the prospect of a field effect transistor combined with quantum tunneling as a means of reducing power consumption while maintaining adequate performance.

Raising mobility through the use of non-silicon materials in the transistor channel remains a favored theme with Gargini but he appeared to push back the prospect of deployment until about 2020.

Gargini discussed compound semiconductor on silicon, as he has done before. But he also discussed the arrival of multigate HKMG III-V devices on silicon substrates arriving by 2020. However, he also discussed the need to optimize for power consumption rather than performance.

Paolo Gargini

Gargini raised the prospect of band-gap engineering to produce tunneling FETs based on germanium in the channel as an intermediate or alternative step to introducing indium arsenide (InSb).

Previously, the challenge had been perceived to be how to design for the maximum on-current while tolerating or reducing the leakage current, Gargini said. Nowperhaps infused by a new awareness of power efficiency at IntelGargini proposed the goal to be to minimize the leakage current and in particular the sub-threshold impact on device performance.

Indeed Gargini raised the prospect of band-gap engineering to produce tunneling FETs based on germanium in the channel as an intermediate or alternative step to introducing indium arsenide (InSb) but he also appeared to push out production to some time before but close to 2020.

At the same event a year before, Gargini had said that compound semiconductors in silicon could be an option in 2015.

When questioned about this apparent inconsistency Gargini said: "We put these things on the shelf. It is up to others to decide when to use them. They may be held for two, three, four years." Gargini gave the example of high-K metal-gate technology at Intel, which was ready in 2005, but for which volume production was delayed a couple of years.

The over-riding message was that while 1970 to 2000 had been 30 years of geometric scaling and "easy riding" the next decades would be far tougher requiring complex materials engineering. He pointed out that as silicon transistors have shrunk from 90nm to 32nm the germanium doping in the channel has gone from 17 percent to 40 percent. It is not difficult to imagine germanium channel transistors with the high mobility that implies.

Gargini was clearly taken with the prospects for the tunneling FET flashing up pictures of him talking with Leo Esaki, a winner of the Nobel prize for physics in 1973 for his work on quantum tunneling. Gargini also referenced a paper entitled "Prospects of a tunneling green transistor for 0.1-V CMOS" presented at the International Electron Devices Meeting in 2010 by Chenming Hu and others.

When asked about graphene in the channel, another hot research topic, he said: "It's perfect across 100?ms but very imperfect on a 12-inch wafer; too many defects. It's going to take 15 years to get it right."

- Peter Clarke
??EE Times





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