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Leakage power: A growing concern for designers

Posted: 05 May 2011 ?? ?Print Version ?Bookmark and Share

Keywords:leakage power? subthreshold-driven? local V<sub>T</sub> variations? leakage power estimation?

With increased use of mobile electronic products worldwide, controlling power consumption remains a daunting challenge for chipmakers determined to scale semiconductor process technologies and add features to ICs. Two kinds of power constitute this consumption: active (Pactive ~ CV2f), which is the power used as the device performs its various functions, and leakage (Pleakage ~ IV), which is the power consumed by unintended leakage that does not contribute to the IC's function.

Leakage power has become a top concern for IC designers in deep submicron process technology nodes (65nm and below) because it has increased to 30-50 percent of total IC power consumption. In addition, the leakage problem is worse than generally thought because the simple, traditional leakage power estimation of multiplying the average transistor leakage by the transistor width of the entire IC grossly underestimates actual product leakage.

Leakage power is primarily the result of unwanted subthreshold current in the transistor channel when the transistor is turned off. This subthreshold-driven leakage power is strongly influenced by variations in the transistor threshold voltage VT (the voltage applied to the gate electrode that turns on the transistor). Transistor threshold voltage variation can be separated into two groups, global variation and local variation.

Global variation includes VT variation due to systematic process variations across a wafer or between different wafers. Examples include non-uniformities in doping, gate length and film thickness (gate oxide, gate poly or metal, spacer, etc.). These systematic variations can be reduced by using a combination of optimized process flows, correction by applying adjusted bias conditions at sort, and device accounting through performance binning.

Local VT variations are not systematic but random, and some cannot be reduced by process optimization. The causes include random dopant fluctuations (RDFs) in the transistor channel, transistor gate line edge roughness, poly or metal gate granularity, and nanoscopic variations in gate oxide thickness. A primary contributor of local VT variations in deep submicron technologies is RDFs, which are generally considered to cause over 70 percent of local VT variations at the 65nm technology node, and these RDFs are becoming more significant as transistor channels become smaller.

Local VT variations occur across a very short distance and are quantified using VT measurements on sets of adjacent, matched transistors. This threshold voltage variation between adjacent transistors, called VT mismatch or sigma-VT (�VT), requires a statistical approach to product design to account for the random fluctuations of device characteristics.

To demonstrate the effects of �VT on total product leakage, consider Figure 1, which illustrates the VT distribution of two groups of 1,000,000 transistors with different values of local VT variation (�VT). While both VT distributions are symmetric Gaussian distributions, the set of transistors with larger �VT has a much wider distribution from higher to lower threshold voltages.

VT distribution

Figure 2 shows the distribution of leakage power from the same two sets of transistors. The leakage power dissipated by a given transistor is given by P(VT) = VCC*IOFF (VT), where VCC is the applied voltage and Ioff is the leakage current for a transistor with this value of VT. The total leakage power dissipated by a group of transistors (such as a product) is therefore the product of the statistical distribution of VT and the leakage power function P(VT).

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