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Software expands verification interoperability

Posted: 13 May 2011 ?? ?Print Version ?Bookmark and Share

Keywords:verification interoperatibility? universal verification methodology? SystemVerilog?

SpringSoft Inc., a global supplier of specialized IC design software, announces comprehensive support for the Universal Verification Methodology (UVM) with its Verdi Automated Debug System. The Verdi software adds UVM source code and new transaction recording capabilities to its existing HDL debug platform, making it easier for engineers to visualize and debug the complex SystemVerilog testbench structures required to test sophisticated system-on-chip (SoC) devices.

UVM is becoming an industry standard approach to ensuring the reusability and interoperability of testbench code (also referred to as verification IP) integrated from multiple sources or developed using different methodologies. The Verdi UVM capabilities are enabled within the system's unified testbench and design debug environment for more efficient recording and viewing of transaction data beyond what is supported by the current UVM infrastructure. With the ability to visualize a broader range of information between the testbench and design under test at the transaction level, Verdi users have a more complete picture of their environment, which is especially critical during detailed regression testing phases.

"Just as SystemVerilog provides a compelling advantage in addressing verification complexity, UVM provides the infrastructure for greater verification interoperability," says Thomas Li, director of product marketing at SpringSoft. "Our UVM implementation combines the proven capabilities of Verdi with enhanced UVM transaction recording that extracts more information critical to debug. This gives engineers a more natural way to better understand and analyze testbench activities and determine whether problems originate in the testbench or the design."

SpringSoft implemented full UVM source code support with the industry standard SystemVerilog library. In addition, SpringSoft provides a custom SystemVerilog file in the Verdi system to transparently record all UVM transactions into the company's defacto standard Fast Signal Database (FSDB) for a complete record of the traffic between testbench components. The transaction data can be used within the existing Verdi waveform tool or in a new Unified Modeling Language (UML)-based sequence diagram view. The automated mechanism eliminates the need for manual recording processes, such as the output of transactions as text messages and instrumentation of testbenches to print transactions into a text file.

The new UVM testbench debug capabilities utilize the feature-rich transaction-level infrastructure of the Verdi environment enabling engineers to debug both the testbench and design efficiently at post-simulation. Key features include a tabular spreadsheet view for highlighting and filtering of transactions, easy-to-use class browsers for navigating testbench hierarchy, and automated tracing through source code to identify the origin of testbench problems.





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