Logic chip supports high-performance networks
Keywords:internet protocol? network? switch systems?
The TSE100x1 provides a variety of interfaces including a standard DDR parallel interface, Interlaken Look-Aside (ILA), and PCI Express, and it supports search rates up to 100MSPS for exact match tables up to 1M entries, and associative match tables with widths of 40, 80, 160, 320, and 640 bits with up to 16K entries. With its support of multitables, the TSE100x1 is virtualization-optimized. It also handles wide TCAM lookup functions enabling the ultra-wide TCAM classification needed for OpenFlow switching 1.1 support in hardware.
"Algo-Logic's layer 2-7 packet processing solutions enables the offload of packet processing algorithms into logic.�Algo-Logic's low-latency packet processing IP cores increase throughput in datacenters and lower latency in trading applications," said Dr. John Lockwood, founder and CEO of Algo-Logic.
"We have found that Tabula's ABAX 3PLD devices with their 5.5 MBytes of 8-ported and 16-ported memory are an ideal cost-effective programmable platform for implementation of packet processing functions. They provide the capacity, bandwidth, and memory granularity for a new and more effective approach to associative lookups," Lockwood added.
"Whether we are talking individual Ethernet packets, the entire Internet, or DNA chains, the world is become increasingly search-centric," said Marc Miller, senior marketing director of Tabula. He added, "The combination of Spacetime breakthrough price/performance and Algo-Logic's expertise in packet processing is enabling a new kind of search engine which are flexible, cost effective and support the rapidly evolving requirements of these applications."
The TSE100x1 device will be offered in Q3, 2011 and the demonstration board is available now.
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