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EDA supplier claims industry's first hierarchical 3D extractor

Posted: 23 May 2011 ?? ?Print Version ?Bookmark and Share

Keywords:hierarchical? 3D extractor? post-layout verification?

Silicon Frontline Technology Inc. (SFT) declared that it has developed H3D, a commercial hierarchical 3D extractor for post-layout verification that the company touts as an industry first.

Campbell, California-based SFT said H3D offers hierarchical parasitic extraction, hierarchical netlisting, unlimited capacity and field-solver accuracy. The tool works with design flows from leading EDA suppliers, according to SFT.

"Post-layout verification is a major bottleneck in today's leading-edge designs," said Yuri Feinberg, CEO of SFT, in a statement. "With the introduction of H3D, this bottleneck is removed by providing an accurate extractor that runs with sub-linear performance and delivers a hierarchical output which enables post-layout simulation speed up."

According to SFT, H3D is suited for array-based and repetitive design structures, including memories, FPGAs and image sensors. The tool's extraction performance is sub-linear, which ensures that as design size grows, extraction performance improves.

SFT said H3D's hierarchical extraction results are design-dependent, but claimed that the company has demonstrated performance improvements from 20-120x when compared to flat extraction.

The extraction tool is built on a hierarchical random walk algorithm, giving users the ability to specify the accuracy required on a net-by-net or block-by-block basis, SFT said. H3D provides unlimited capacity due to its hierarchical extraction and parallelization, the company added.

The hierarchical output supports R, C, distributed RC and RCCc, according to SFT.

H3D is shipping early in the third quarter. Pricing information was not provided.

- Dylan McGrath
??EE Times

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