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Power optimization tool reduces power by 60%

Posted: 31 May 2011 ?? ?Print Version ?Bookmark and Share

Keywords:power optimization? power analysis? RTL analysis?

Calypto Design Systems Inc. has released the version 5.0 of its PowerPro Platform, a full suite of RTL power optimization tools proven to reduce power by up to 60 percent on multimillion gate designs. The PowerPro Platform features new RTL power analysis capabilities, production-proven optimization techniques for reducing dynamic and leakage power in the logic, memory, and embedded processor sections of a SoC, and provides sequential formal equivalence checking.

Version 5.0 of the PowerPro Platform improves turnaround time by 2x and includes new usability features such as advanced reset-logic insertion, bottom-up flow support, a stronger sequential analysis engine for PowerPro MG (Memory Gating), and the ability to read the Fast Signal Database (FSDB), which eliminates the need for large Value Change Dump (VCD) files. In addition, each PowerPro module can run in a fully automatic or a manual mode, giving users the flexibility to select the use mode most appropriate for each section of their design. The manual use mode graphically illustrates the power reducing RTL modifications that can be made, but leaves it up to the user to decide how best to implement them.





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