Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Chip solution automates IC design planning

Posted: 07 Jun 2011 ?? ?Print Version ?Bookmark and Share

Keywords:automoated? planning solution? custom IC design?

Pulsic Ltd has unveiled a integrated full-chip solution, said to have top-level functionality, is designed for custom, analog and mixed-signal (AMS) ICs automated planning.

According to Pulsic, the solution is based on the company's Unity technology that is used by top design companies for more than 10 years now. The tool has components for chip planning, power panning, bus and repeater cell planning and signal planning.

Pulsic said the solution is its response to users encountering bottlenecks as custom design complexity continues to increase dramatically. This as large, complex custom IC designs and complex top-level floor planning are forcing digital design teams to spend more time and resources to complete floor plans and DRC-correct top level integration.

Unlike the large custom ICs available in the market today, Pulsic said the solution is the first complete planning tool suite to enable top down and bottom up hierarchical floor planning for custom ICs.

The company claims that the lack of configurability of large custom ICs makes it impossible to complete finer tasks, such as bus/repeater cell planning and insertion or DRC/ LVS top level routing. As a result, semiconductor companies are forced to license the whole flow as a single 'seat' from an ASIC tool vendor.

"Each component of the Pulsic Planning Solution has two advantages: technological advances provide increased productivity, and each can be purchased in any combination, making critical functionality highly configurable for each member of the design team," said Pulsic founder and CEO Mark Williams.

The solution guides users through the entire floor planning process, from initial blackbox (or prototype) to the final layout. The flow encompasses all the necessary steps and allows users to quickly adopt each netlist revision and engineering change order (ECO). This result in a truly hierarchical platform, and with all components integrated to each other and with real custom design flows, OpenAccess (OA), Cadence (CDBA) and industry standard (LEF/DEF/Verilog), Pulsic said.

It added that the solution offers maximum productivity and requires minimum training from the users as it is completely integrated, with a single executable, removing data translation issues and maximizing productivity.

The Unity's ECO technology in the solution allows rapid adoption of changes and new revisions into the design without the need to start again. ECO technology ensures that previous work is never wasted and that designers always have a head start on the next revision.





Article Comments - Chip solution automates IC design pl...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top