Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Simulation tool offers Xilinx FPGA verification

Posted: 08 Jun 2011 ?? ?Print Version ?Bookmark and Share

Keywords:simulation tool? verification? development boards?

MathWorks Inc. has announced the availability of EDA Simulator Link 3.3 with new FPGA-in-the-loop (FIL) capabilities for Xilinx FPGA development boards. FIL enables engineers to verify their designs at hardware speeds while using Simulink as a system-level test bench.

The introduction of FIL adds to the comprehensive set of HDL verification options that EDA Simulator Link supports for algorithms created in MATLAB and Simulink. FPGA-based verification provides higher run-time performance than is possible with HDL simulators and increases confidence that the algorithm will work in the real world.

The simulator verifies HDL implementations of MATLAB code and Simulink models using FPGA development boards for both Spartan and Virtex class devices, including the Virtex-6 ML605 development board. The tool is also works with Mentor Graphics ModelSim, Mentor Graphics Questa, and Cadence Design Systems Incisive Enterprise Simulator and generates TLM 2.0 components for SystemC virtual prototyping environments.





Article Comments - Simulation tool offers Xilinx FPGA v...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top