Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

EDA faces cost challenges

Posted: 08 Jun 2011 ?? ?Print Version ?Bookmark and Share

Keywords:EDA? design automation? IC design process?

EDA market analyst Gary Smith EDA Inc. (GSEDA) predicts that design automation tools will become a $6.6 billion industry by 2015. However, this will only happen if the industry is serious in taking on the responsibility of developing design tools that will enable the IC design process. The industry also faces the challenge of developing tools "at a design cost that allows the ecosystems to operate at a profit," according to GSEDA.

"This is not about cost of EDA toolsthat's lunch money," said a principal analyst from GSEDA. "What I'm talking about is the level of automation; the costs are in the engineers to do the design."

The GSEDA analyst added, "if we can keep the cost of designing a SoC below $25 million the VCs will start funding semiconductor startups again." He said if that cost is above $50 million, even IDMs will not be able to afford to do many designs.

GSEDA was adamant in stating that the EDA industry, as a whole, is responsible for developing a level of automation that allows the design process to be affordable. That cannot be done with today's makeup of design teams.

Today's design team size ranges from 100 to 200 engineers, said GSEDA. The design team size "for 104 million gates should be 30 hardware design engineers for a cost of $18.7 million," GSEDA said. The company offered a divide and conquer approach by bringing down the number of blocks a designer handles from the usual 25 to 35 today down to 5. "Anything over that slows down the design significantly and drives up the cost."

According to GSEDA, using a platform design methodology can reduce the number of engineers assigned per block among designers, integrators and verification engineers needed from 36 to 24 for a 100 million gate design. As far as tools are concerned Smith ideally an EDA tool should be able to handle 20 million gates in "average" high-end designs.

The market analyst's number one peeve: "We still have far too many R&D engineers that don't have the slightest idea how design engineers use their tools." The company calls on all industry participants to get involved in the 'software productivity' problem, lest the EDA tools become irrelevant in chip designs. As far as the "big three" EDA companies are concerned, GSEDA rates Synopsys as the No. 1 EDA company, followed by Mentor Graphics and Cadence respectively.





Article Comments - EDA faces cost challenges
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top