Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

IC design tool available for prototyping

Posted: 17 Jun 2011 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? 28nm? SiGe process?

STMicroelectronics, through the silicon brokerage services of Circuits Multi Projets (CMP), has made available its CMOS 28nm process for prototyping to universities, research laboratories and companies.

Aside from the design process, STMicrolectronics said CMP is also offering 65nm and 130nm SOI (Silicon-On-Insulator) and the 130nm SiGe processes.

To date, 170 universities and companies have received the design rules and design kits for the 90nm CMOS process, according to STMicroelectronics. In addition, more than 200 universities and companies (60 percent in Europe, 40 percent in Americas and Asia) have received design rules and design kits for its 65nm bulk and SOI CMOS processes. The 45/40nm CMOS is still being deployed.

"There has been a great interest in designing ICs in these processes, with about 300 projects having been designed in 90nm (phased out in 2009), and 200 already in 65nm," CMP director Bernard Courtois said.

Courtois added that 60 projects have already been designed in 65nm SOI, noting that some of the users are top universities in Europe, in the USA and in Asia.

"This very exciting program perfectly illustrates our strong involvement with the education and research communities. It is essential that university students and researchers can have access to the most advanced technologies, which we have been providing in cooperation with CMP for two decades," said Patrick Cogez, STMicroelectronics director for universities and external relations and front-end technology and manufacturing.

STMicroelectronics' program for universities ensures the company's access to new talents. The company has already released to universities and companies previous

CMOS generations such as 45nm (introduced in 2008), 65nm (introduced in 2006), 90nm (introduced in 2004) and 130nm (introduced in 2003).

The CMP multiproject wafer service allows organizations to obtain small quantitiestypically from a few tens to a few thousand unitsof advanced ICs. The cost of the 28nm CMOS process has been fixed to 15,000 Euros/mm2, with a minimum charge of 1mm2. Users can order a die area as small as 1mm2.





Article Comments - IC design tool available for prototy...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top