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Rambus details memory clocking tech

Posted: 17 Jun 2011 ?? ?Print Version ?Bookmark and Share

Keywords:memory clocking? clocking technology? feed-forward architecture?

Rambus Inc. used the VLSI Circuit Symposium in Kyoto, Japan to explain its efforts to develop a fast power-on, low-power clocking technology, which it claims will facilitate the design of a new family of memory devices.

The technology is capable of transitioning from a zero-power idle state to a 5+Gbps data transfer rate in approximately 5ns while achieving active power of only 2.4mW/Gbps, according to Rambus.

The new approach, developed by Rambus Labs, uses a calibrated feed-forward architecture to achieve extremely fast turn-on and turn-off, simplifying system design and significantly reducing overall system power requirements, Rambus said.

The technology is implemented in a 40nm low-power CMOS process, according to the company.

"Through this work, we have dramatically reduced system complexity and have saved substantial power while increasing performance to more than 5Gbps per differential link," said Jared Zerbe, technical director at Rambus. "When incorporated into a SoC-to-memory interface, or SoC-to-SoC link, this development can significantly reduce the memory system power and time-to-first access, driving us closer to the vision of energy proportional computing."

Zerbe said Rambus Labs would continue to develop the technology, pushing speed and performance. Asked when the technology might be available for commercialization, Zerbe described it as still in the pure research phase.

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