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NEC targets U.S., European design houses with HLS tool

Posted: 23 Jun 2011 ?? ?Print Version ?Bookmark and Share

Keywords:design automation? behavioral synthesis? IC designs?

NEC Corp. is determined to penetrate the U.S. and European markets with its reliable high-level synthesis design automation tools, its export drive bolstered by over 20 years of research in behavioral synthesis of IC designs.

The company's researchers took the floor at the recently held Design Automation Conference in San Diego and showed potential customers their latest iteration of CyberWorkBench. They later moved to the San Francisco Bay area, inviting a number of major corporations based there to sample the tool.

"Design houses are clamoring for high-level chip synthesis tools that address both data and control paths of their designs," said Benjamin Carrion Schafer, assistant manager, System IP-Core Research Lab, Central Research Laboratories, NEC Corp.

Kazutoshi Wakabayashi, senior principal researcher, embedded systems solution division at NEC, listed a number of Japanese firms that have accepted NEC's CyberWorkBench for high-level synthesis design flows. They include NEC Electronics, which has produced a "billion dollars worth" of chips for internal use, Panasonic, Toyota, JAXA, Toshiba, Hitachi, Advantest, JVC and Fujitsu.

"We began our efforts at engaging the U.S. at last year's DAC and are continuing to attract the likes of Intel with training course for test driving the tools," said Schafer

Over the summer, NEC plans to reveal more than an "order of magnitude" cheaper version of the current full CyberWorkBench suite, specifically for designing with FPGAs.

Wakabayashi has been at his quest to develop high-level synthesis tools since the 1980s and in 1993 his NEC researchers taped out the first IC with a C-level synthesis tool. A number of vendors, among them Mentor Graphics and Forte, have provided parts of high-level synthesis solutions that raise the level of abstraction from the RTL and provide an architectural approach to synthesis.

The new version of Forte's Cynthesizer HLS, for example, includes an upgraded version of its Interface Generator with the ability to automatically generate interfaces that incorporate clock domain crossing (CDC) circuits.

In a recent official Forte blog, the following remarks echoed the travails involved in going from RTL to ESL: "The fact is that ANSI-C cannot handle real design and verification needs and the designers in Japan know it. Those surveyed at SystemC 2010 Japan said their SystemC usage falls into these five categories (multiple answers allowed): 52.7 percent HLS; 44.8 percent Functional verification; 33.5 percent Virtual platform/software design; 30.5 percent Architecture design; and 1.5 percent Other.

So why use SystemC instead of ANSI-C? It is true that ANSI-C and SystemC can both be synthesized, but that's not where the problem lies. The problem is in the modeling and design environment that you need to build. Sure you can synthesize a serial algorithm in ANSI-Cbut real designs have hierarchy, concurrency, control and complex interfaces where data is exchanged in parallel. Let's face itANSI-C just doesn't cut it. SystemC was developed specifically to rectify ANSI-C's shortcomings for hardware design."

NEC claims that its CyberWorkBench is aimed at those users of SystemC who are clamoring for HLS tools. Earlier this year, NEC partnered with EDATechForce, LLC to bring the CyberWorkBench into the North American market.

"We are very impressed with how quickly EDATechForce has absorbed the needs of our market and brought potential customers to our attention. I think this can be attributed to their unique business model of bringing synergistic technologies together for the benefit of our mutual customers," said Wakabayashi.

"One of CWB's most important capabilities is automatic design space exploration, which enables design teams to realize these benefits and meet or exceed their ever shrinking design cycles," said Carl DeSalvo, president and CEO of EDATechForce.

At an ESL panel at DAC this year, Gady Singer, vice president of Intel's Architecture Group and general manager of the SOC Enabling Group said that it's time to push abstraction to a higher level: "Intel has been doing RTL for 20 years, it's time to move on, but unfortunately, ESL tools are not at critical mass yet." Among the required developments for ESL to take off are standards, an improved ECO (engineering change order) flow, better ESL model validation, and improved formal equivalence capacity between ESL and RTL, according to Singer.

"The problem is that today hardware designers, software developers, verification engineers and systems engineers all have different goals and requirements," said panelist Simon Bloch, vice president and general manager of Mentor Graphics' Design and Synthesis Division.

NEC's Wakabayashi aims to enable all parties in the design flow to talk the same language with the CyberWorkBench platform, claiming the platform's 20+ years of R&D heritage a solid advantage.

- Nicolas Mokhoff
??EE Times

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