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PCIe Gen 4 to deliver 16GTps throughput

Posted: 27 Jun 2011 ?? ?Print Version ?Bookmark and Share

Keywords:PCIe Gen 4? transreceivers? PHY design?

At least one more high-speed version of PCI Express can be extracted from copper links before the anticipated shift to optical interconnects, according to the PCI Special Interest Group. Scheduled to appear in products in about four years, PCIe Gen 4 could boast rates of no less than 16GTransfers/s.

"The initial report we got yesterday is that PCI Express 4.0 is feasiblewe have to work out the details, but it is feasible," said Al Yanes, president of the PCI SIG, speaking in a press briefing at the group's annual developers conference.

An exploratory group including members from AMD, Hewlett-Packard, IBM and Intel are conducting simulations using chip, channel, packet and socket data. They have determined throughput of at least 16GTps is possible and are expected to deliver a final report before the end of the year.


"We think we can eke out one more turn of the crank out of copper, so we are not looking at optics yet," said Ramin Neshanti, chairman of the PCI SIG's serial communications working chair.

It took the PCI SIG about four years to hammer out its 8GTps PCIe Gen 3 spec which required new signal encoding and equalization schemes. The Gen 4 spec should take a similar period, but this time the focus will be less on silicon and more on the board-level channels through which signals pass, Neshanti said.

Specifically, Gen 4 will probably be limited to distances of about eight to twelve inches compared to 20 inches for Gen 3. Engineers wanting longer reaches will need to use repeaters, a potential growth area for PCIe silicon.

The Gen 4 boards may need to use new materials, via designs and backwards-compatible connectors designed for improved signal integrity to reduce impedance discontinuities. "We think we have achieved about as much as we can scaling silicon," said Neshanti who also serves as an I/O standards manager at Intel.

That's a big shift for the PCIe community which has not previously required major changes of board makers. Typically the PCI SIG has thrown its hardest problems to chipmakers such as AMD, Intel, NEC and others to ease problems for its less technically sophisticated supply chain among high volume PCB and system makers.

Nevertheless, some significant silicon shifts are ahead. Transceivers for Gen 3 were the first to use techniques to massage signals, adopting single-tap decision feedback equalization (DFE).

Gen 4 transceivers will need to use multitap DFE. How many taps they will need is not yet clear.

"There also will be heavy investments needed from test equipment vendors to do some very creative probing solutions either on chip or somehow as an add-in," said Neshanti. Agilent, LeCroy and Tektronix are among the testers involved in the work, "but we don't know which will step up first," he said.

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