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Pin FMEA for AUP family

Posted: 11 Jul 2011 ?? ?Print Version ?Bookmark and Share

Keywords:NXP? CMOS logic?

The NXP ultra-low-power (AUP) CMOS logic 74AUP1G/2G3Gxxx family is designed for low-power applications. These low-voltage, Si-gate CMOS devices are touted to have the industry's lowest dynamic power consumption in a logic device.

Operating over a very wide supply range of 0.8 V to 3.6 V, AUP devices are ideally suited for use in mixed-voltage applications. Schmitt-trigger action at all inputs improves noise immunity by making the circuit tolerant to slower input rise and fall times across the entire range of supply voltage.

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