FPGAs/PLDs??
Pin FMEA for AUP family
Keywords:NXP? CMOS logic?
The NXP ultra-low-power (AUP) CMOS logic 74AUP1G/2G3Gxxx family is designed for low-power applications. These low-voltage, Si-gate CMOS devices are touted to have the industry's lowest dynamic power consumption in a logic device.
Operating over a very wide supply range of 0.8 V to 3.6 V, AUP devices are ideally suited for use in mixed-voltage applications. Schmitt-trigger action at all inputs improves noise immunity by making the circuit tolerant to slower input rise and fall times across the entire range of supply voltage.
View the PDF document for more information.
| Related Articles | Editor's Choice |
Article Comments - Pin FMEA for AUP family
Visitor(To avoid code verification, simply login or register with us. It is fast and free!)
?
Top Ranked Articles
?
Webinars
Visit Asia Webinars to learn about the latest in technology and get practical design tips.
All rights reserved.