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Circuit allows sample-and-hold amplifier test

Posted: 11 Jul 2011 ?? ?Print Version ?Bookmark and Share

Keywords:sampling circuit? digitizing? ADC?

Sample-and-hold amplifiers sample an analog voltage and hold it until an ADC can digitize it. A perfect sampling circuit holds a voltage until digitizing is complete. Hence, the amplifier's output is identical to its input. Real sample-and-hold amplifiers, however, can gain or lose voltage, producing an error. Offset voltages in amplifiers cause a static additive error. Further, there occurs a specific additive error, the so-called voltage pedestal, which originates within the transition from the sample state to the hold state because of a parasitic charge transfer to the hold capacitor.

A sample-and-hold amplifier uses an analog switch to connect a signal to a holding capacitor. When the switch closes, thus having low resistance, the capacitor charges to the sampled input voltage. During the hold time, when the switch has high resistance, the sampling capacitor holds the voltage until the ADC digitizes it.

During the transition from low to high switch resistance, a parasitic charge injection, mainly from the gate of the switch to the hold capacitor, continues to charge the capacitor until the switch's control voltage reaches a steady logic level. The injected charge produces an error voltage at the capacitor.

Additional errors may occur during the hold time. Leakage and bias currents in the amplifier combine with tens of picoamps of leakage current in the switch and capacitor to cause the capacitor to charge or discharge during hold time.

By applying a logic-control signal with a duty cycle of D and 1 每 D, you can measure a mean output voltage difference, [忖VOUT]=[VOUT每VIN], which the following equations show:

[忖VOUT]=VSTAT+ (1 每 D)VINJ+?(1 每 D)嚙?VDROPPEAK, and [忖]=VSTAT+DVINJ+?D嚙碾DROPPEAK,

where 忖VOUT and 忖 are the output-voltage differences for D and 1 每 D, respectively; VSTAT is the steady output-voltage difference for a selected value of the reference input voltage, D is the duty cycle, VINJ is the voltage pedestal, and VDROPPEAK is the peak voltage drop.

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Figure 1: A sample-and-hold amplifier's holding capacitor experiences a voltage drop due to leakage and bias currents plus a voltage step, which results in a difference between the amplifier's output and input voltages.

Figure 1 shows how the voltages in the equations change over time. If you apply a complementary control waveform with a duty cycle of 25%, you can measure another dc component of the sample-and-hold amplifier's output voltage.

Finally, when the sampling switch is continuously on, you can measure the VSTAT voltage, which is a real dc voltage. VOUT and contain a waveform superimposed onto a selected value of the reference voltage. Thus, you should measure the mean values of these voltages using a series resistor with a value of, say, 10 k(次).

Testing sample-and-hold amplifiers
Multiplying the voltage pedestal, a simple rectangular waveform, by the duty cycle yields the average value. In contrast, the voltage-drop waveform appears as a sawtooth. Its mean rises as one-half of the duty cycle squared. The peak-voltage-drop value denotes a hypothetical voltage drop at the end of a whole period, T, of the SAMPLE/ logic-control waveform.

You can use the previous equations to find the values of the voltage pedestal and the peak voltage drop. A 75% duty cycle is a convenient value.

The following equations are valid for this duty cycle:

VINJ=6[忖VOUT] 每 2/3[忖] 每 16/3VSTAT, and VDROPPEAK=16[每[忖VOUT]+1/3[忖]+2/3VSTAT].

You must find the optimal repetition rate, fREP, of the logic-control signal.

As the optimal repetition rate increases, the difference in output voltage from the input is almost purely due to dc voltage offset plus the voltage pedestal:

( 每 V STAT)/(VOUT 每 VSTAT)>3.

The following equation finds the maximum value for the optimal repetition rate: fREP≒(0.01/4)℅1/(tON 每 tOFF), where tON and tOFF are the on and off times, respectively.

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