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Design suite supports 28nm 7 series

Posted: 11 Jul 2011 ?? ?Print Version ?Bookmark and Share

Keywords:28nm? 7 series families? design suite?

Xilinx Inc. has released the ISE Design Suite 13.2 that supports the 28nm 7 series families including the Virtex-7 VX485T device.

According to Xilinx, this version of the ISE design suite gives up to 25-percent performance increase in designs targeting Virtex-7 2000T devices. Virtex-7 2000T devices claim to be the industry's largest density FPGAs built using Stacked Silicon Interconnect technology.

The software also has enhancements to the PlanAhead design and analysis tool, providing partial reconfiguration support for Virtex-7 and Kintex-7 FPGAs, and front-to-back, integrated project management environment for improved productivity in designs targeting Spartan-6 FPGAs, Virtex-6 FPGAs, their defense grade counterparts, and all three 7 Series families including initial support for the low-cost Artix-7 family. The PlanAhead tool also gives designers the tools they need to facilitate global-team design; give rapid feedback on key design considerations; access to best practices for low-power optimization using the XPower Estimator tool; reduce power through intelligent clock-gating.

The updates to the software's XPower Estimator (XPE) tool enables designers to make power-consumption predictions with a high-level of accuracy and see how Xilinx's choice of TSMC's high-k metal gate (HKMG) high performance low power process, and a unified FPGA architecture across families, deliver the lowest power of any FPGA in their class in most typical designs.

In further support of Xilinx's Plug-and-Play IP initiative, the ISE design suite 13.2 enables Advance eXtensible Interface (AXI) interconnect support in CORE Generator system to build higher performance point-to-point architectures. Design teams building their own AXI compliant IP can now run simulations of the AXI interconnect protocol using the optional AXI bus functional model (BFM) verification IP to easily ensure all interface transactions are working properly (See User Guide: AXI Bus Functional Model v1.1 ). The AXI BFM is now available for ISim as well as Cadence, Mentor and Synopsys simulators. Users can now also access AXI_PCIe cores from the Embedded Development Kit in designs targeting Virtex-6 and Spartan-6 FPGAs. Additionally, the ChipScope AXIMonitor core in the Embedded Development Kit now supports monitoring of the AXI3 interface and includes an optional AXI Protocol Checker. The AXI Protocol Checker is designed around the ARM SystemVerilog assertions and supports 39 Ready/Valid handshake checks.

Partial Reconfiguration support for Kintex-7 and Virtex-7 families is now also available in PlanAhead. Partial Reconfiguration dynamically modifies logic blocks while the remaining logic operates without interruption. This means designers can use either Virtex-7 or Kintex-7 devices to build flexible systems that are able to swap functions and perform remote updates while operational. Partial reconfiguration also allows designers to reduce costs and design size by taking advantage of time-multiplexing that ultimately leads to reduced board space and minimizes bitstream storage because smaller, or fewer, devices can be utilized. Smaller and fewer devices can also lead to reductions in system power, while swapping out-power hungry tasks can minimize the FPGA's dynamic power consumption. When Artix-7 family support is rolled in with the release of ISE Design Suite later this year, it will be the first time that Xilinx has offered partial reconfiguration for the entire range of FPGA families in a single generation.

ISE Design Suite 13 is immediately available for all ISE Editions and list priced starting at $2,995 for the Logic Edition and now supports 32 and 64 bit Windows 7. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx web site.

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