Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > T&M

Design tester includes Polyspace analysis

Posted: 13 Jul 2011 ?? ?Print Version ?Bookmark and Share

Keywords:simulink? design verifier?

MathWorks Inc. has announced that its Simulink Design Verifier has been updated to include Polyspace analysis technology for automated error detection in Simulink models.

The Simulink Design Verifier 2.0 integrates Polyspace error detection with existing property proving and test generation capabilities to help reduce the time required to find and fix the root cause of design errors, decreasing the overall cost of verification and validation.

Engineers across the aerospace, automotive, medical and industrial automation and machinery industries can apply model-based design with formal analysis methods provided by Simulink Design Verifier 2.0 to identify design errors in Simulink and Stateflow models without extensive testing or simulation.

Key product features include: a) detection of dead logic, integer and fixed-point overflows, division by zero, and assertion violation; b) blocks and functions for modeling functional and safety requirements; c) test vector generation from functional requirements and model coverage objectives; d) property proving, with generation of violation examples for analysis and debugging; and e) fixed-point and floating-point model support.

Simulink Design Verifier is now available.

Article Comments - Design tester includes Polyspace ana...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top