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Imec reports breakthroughs in DRAM, RRAM

Posted: 15 Jul 2011 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? RRAM? memory technology?

Imec International has announced that in the frame of its research on future memory architectures, it has made breakthroughs for both DRAM and RRAM memories.

One of the major technical challenges for the DRAM industry is the difficulty to maintain target leakage currents a lower effective oxide thickness (EOT) to meet the DRAM capacitor scaling roadmap. Imec was able to demonstrate a RuOx/STO/TiN stack that showed a 100x reduction in leakage with DRAM MIMcap compatible dielectrics at 0.4mm EOT. Imec was then able to further the reduction to 10x more by optimizing the stack. This resulted in a record leakage density (JG) of 2x10-8A/cm2 at 0.4nm EOT. This allowed a path to demonstrate a further potential through lowering the trap density, to a theoretical leakage current density (JG) limit for trap-free STO of 10-15A/cm2 at ~0.4nm EOT. The results showed that the STO-based stack is a promising technology for DRAM scaling.

RRAM is also seen as the future for next-generation non-volatile memories. In RRAM, a dielectric, which is normally insulating, can be made conductive through a filament or conduction path formed by applying a sufficiently high voltage. Imec now has made breakthroughs in understanding the properties of the filaments. Imec established a.o. that the minimal achievable current after reset depends on the physical nature of the filaments, resulting in a direct method to predict that current from the filament properties. With these results, it is now possible to choose the desired properties of the filaments to ensure a stable RRAM operation.

The results were obtained in cooperation with imec's key partners in its core CMOS programs Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, Hynix, Fujitsu and Sony.

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