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JEDEC announces DDR4 standard specs

Posted: 24 Aug 2011 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? DDR4 standard? I/O voltage?

JEDEC Solid State Technology Association, developer of DDR standards, has released the design and features of the double data rate 4 (DDR4) standard.

The DDR4 standard is expected to be published in mid-2012 and will offer significant advancements in performance with reduced power usage as compared to previous generation technologies, said JEDEC. When published, the DDR4 standard will be available on the company's website.

DDR4 is being developed with a range of features designed to enable high-speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. Its speed, voltage and architecture are all being defined with the goal of simplifying migration and facilitating adoption of the standard.

The company has revealed that a DDR4 roadmap has been proposed and this will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. DDR4 will help protect against technology obsolescence by keeping the I/O voltage stable, JEDEC said.

The per-pin data rates, over time, will be 1.6GT/s to an initial maximum objective of 3.2GT/s. With DDR3 exceeding its expected peak of 1.6 GT/s, it is likely that higher performance levels will be proposed for DDR4 in the future.

Other performance features planned for inclusion in the DDR4 standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667MHz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes.

The standard will include a new JEDEC POD12 interface standard for DDR4 (1.2V). The DDR4 also covers three data width offerings: x4, x8 and x16. It has differential signaling for the clock and strobes.

The DDR4 standard has a new termination scheme where the DQ bus shifts termination to VDDQ, which should remain stable even if the VDD voltage is reduced over time. The standard includes a nominal and dynamic ODT, which improves the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin. It has a burst length of eight and burst chop of four and contains data masking.

The standard also features a DBI that can help reduce power consumption and improve data signal integrity. This feature informs the DRAM as to whether the true or inverted data should be stored.

The new CRC for data bus of the DDR4 standard will enable error detection capability for data transfers, which is especially beneficial during write operations and in non-ECC memory applications. The DDR4 standard also contains a new CA parity for command/address bus, which provides a low-cost method of verifying the integrity of command and address transfers over a link, for all operations; and (11) it is a DLL off mode supported.

JEDED is planning to host a DDR4 technical workshop following the publication of the standard. More information and details will be announced coincident with publication.

"Numerous memory device, system, component and module producers are collaborating to finalize the DDR4 standard, which will enable next-generation systems to achieve greater performance with lower power consumption," said Joe Macri, chairman of JEDEC's JC-42.3 subcommittee for DRAM memories.

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